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PDF AM41LV3204M Data sheet ( Hoja de datos )

Número de pieza AM41LV3204M
Descripción Static RAM
Fabricantes AMD 
Logotipo AMD Logotipo



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Am41LV3204M
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 30119 Revision A Amendment +1 Issue Date June 10, 2003

1 page




AM41LV3204M pdf
PRELIMINARY
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Option
Standard Voltage
Range: VCC = 2.7–3.3 V
Max Access Time (ns)
Max. CE# Access (ns)
Max. Page Access Time (tPACC)
OE# Access (ns)
Flash Memory
Am41LV3204M
10
100
100
30
30
Note: See “AC Characteristics” for full specifications.
MCP BLOCK DIAGRAM
VCCf
VSS
A20 to A0
A–1
WP#/ACC
RESET#
CE#f
CIOf
A20 to A0
RY/BY#
32 M Bit
Flash Memory
DQ15/A-1 to DQ0
SRAM
10
70
70
N/A
35
SA
LB#s
UB#s
WE#
OE#
CE1#s
CE2s
CIOs
VCCs/VCCQ VSS/VSSQ
AA017totoA1A90
4 M Bit
Static RAM
DQ15/A-1 to DQ0
DQ15/A-1 to DQ0
4
Am41LV3204M
June 10, 2003

5 Page





AM41LV3204M arduino
PRELIMINARY
Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH, SRAM Word Mode, CIOs = VIH
Operation
(Notes 1, 2)
CE#f CE1#s CE2s OE# WE# SA
Addr.
LB#s
UB#s
RESET#
WP#/ACC
(Note 4)
DQ7–
DQ0
DQ15–
DQ8
Read from Flash
HX
L
X
LH X
L
AIN
X
X
H
L/H
DOUT
DOUT
Write to Flash
HX
L
X
HL X
L
AIN
X
X
H (Note 4) DIN DIN
Standby
VCC ±
0.3 V
H
X
X
XX X
L
X
X
X
VCC ±
0.3 V
H High-Z High-Z
Output Disable
HH X X L X
LLH
H
HH X X X L
L/H High-Z High-Z
Flash Hardware
Reset
HX
X XX X
XL
X XX
L
L/H High-Z High-Z
Sector Protect
(Note 5)
HX
SADD,
L
X
L
HL
X
A6 = L,
A1 = H,
X
X
VID
A0 = L
L/H DIN X
Sector Unprotect
(Note 5)
HX
SADD,
L
X
L
HL
X
A6 = H,
A1 = H,
X
X
VID (Note 6) DIN
A0 = L
X
Temporary Sector
Unprotect
X
H
X
X
XX X
L
X
XX
VID (Note 6) DIN High-Z
LL
Read from SRAM H L H L H X AIN H L
H
LH
LL
Write to SRAM
H L H X L X AIN H L
H
LH
DOUT
DOUT
X High-Z DOUT
DOUT High-Z
DIN DIN
X High-Z DIN
DIN High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address
Input, Byte Mode, SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by 40%.
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “”. If WP#/ACC = VHH, all sectors will
be unprotected.
10
Am41LV3204M
June 10, 2003

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