PDF AM29SL400C Data sheet ( Hoja de datos )

Número de pieza	AM29SL400C
Descripción	Super Low Voltage Flash Memory
Fabricantes	AMD
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No Preview Available ! www.DataSheet4U.com Am29SL400C Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number Am29SL400C Revision A Amendment +5 Issue Date March 3, 2005 1 page Advance Information Table of Contents Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Special Handling Instructions for FBGA Packages ............6 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9 Table 1. Am29SL400C Device Bus Operations ......................... 9 Word/Byte Configuration ........................................................9 Requirements for Reading Array Data .................................9 Writing Commands/Command Sequences ....................... 10 Program and Erase Operation Status ................................. 10 Standby Mode ............................................................................ 10 Automatic Sleep Mode ............................................................ 10 RESET#: Hardware Reset Pin ............................................... 10 Output Disable Mode ................................................................11 Table 2. Am29SL400CT Top Boot Block Sector Address Table ...................................................................................... 11 Table 3. Am29SL400CB Bottom Boot Block Sector Address Table ........................................................................ 11 Autoselect Mode .........................................................................11 Table 4. Am29SL400C Autoselect Codes (High Voltage Method) ................................................................................. 12 Sector Protection/Unprotection ...........................................12 Temporary Sector Unprotect ................................................12 Figure 1. In-System Sector Protect/Unprotect Algorithms.... 13 Figure 2. Temporary Sector Unprotect Operation................. 14 Hardware Data Protection .................................................... 14 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 14 Reading Array Data .................................................................. 14 Reset Command ........................................................................ 14 Autoselect Command Sequence ...........................................15 Word/Byte Program Command Sequence ........................15 Figure 3. Program Operation.......................................................... 16 Chip Erase Command Sequence ...........................................16 Sector Erase Command Sequence .......................................16 Figure 4. Erase Operation ............................................................... 17 Command Definitions ............................................................. 18 Table 5. Am29SL400C Command Definitions .......................... 18 Write Operation Status .......................................................... 18 DQ7: Data# Polling .................................................................. 19 Figure 5. Data# Polling Algorithm................................................. 19 RY/BY#: Ready/Busy# ............................................................. 19 DQ6: Toggle Bit I ..................................................................... 20 DQ2: Toggle Bit II .................................................................... 20 Reading Toggle Bits DQ6/DQ2 ........................................... 20 Figure 6. Toggle Bit Algorithm ....................................................... 21 DQ5: Exceeded Timing Limits ...............................................21 DQ3: Sector Erase Timer ....................................................... 21 Table 6. Write Operation Status ................................................. 22 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 22 Figure 7. Maximum Negative Overshoot Waveform............. 22 Figure 8. Maximum Positive Overshoot Waveform .............. 22 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ............................................................ 25 Figure 10. Typical ICC1 vs. Frequency........................................... 25 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 11. Test Setup ......................................................................... 26 Table 7. Test Specifications ............................................................ 26 Key to Switching Waveforms ............................................... 26 Figure 12. Input Waveforms and Measurement Levels .......... 26 Read Operations .......................................................................27 Figure 13. Read Operations Timings ............................................ 27 Hardware Reset (RESET#) ................................................... 28 Figure 14. RESET# Timings ............................................................. 28 Figure 15. BYTE# Timings for Read Operations ...................... 29 Figure 16. BYTE# Timings for Write Operations.................... 29 Erase/Program Operations ................................................... 30 Figure 17. Program Operation Timings........................................ 31 Figure 18. Chip/Sector Erase Operation Timings .................... 32 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 19. Data# Polling Timings (During Embedded Algorithms) ......................................................................................... 33 Figure 20. Toggle Bit Timings (During Embedded Algorithms) ......................................................................................... 33 Figure 21. DQ2 vs. DQ6 .................................................................. 34 Temporary Sector Unprotect ...............................................34 Figure 22. Temporary Sector Unprotect Timing Diagram................................................................................................ 34 Figure 23. Sector Protect/Unprotect Timing Diagram .......... 35 Alternate CE# Controlled Erase/Program Operations ..................................................................................36 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 24. Alternate CE# Controlled Write Operation Timings ................................................................................................. 37 Erase and Programming Performance . . . . . . . . 38 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 38 TSOP Pin and BGA Package Capacitance . . . . . 38 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 39 TS048—48-Pin Standard TSOP ............................................39 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . .40 FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 8 mm Package .................................................... 40 Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . 41 March 3, 2005 3 5 Page Advance Information Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The com- mand register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the ad- dress and data information needed to execute the command. The contents of the register serve as in- puts to the internal state machine. The state ma- chine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Am29SL400C Device Bus Operations DQ8–DQ15 Read Write Operation Standby WE CE# OE# # RESET# L LH H L HL H VCC ± 0.2 V X X VCC ± 0.2 V Addresses (Note 1) AIN AIN X DQ0– DQ7 DOUT DIN BYTE# = VIH BYTE# = VIL DOUT DIN DQ8–DQ14 = High-Z, DQ15 = A-1 High-Z High-Z High-Z Output Disable L HH H X High-Z High-Z High-Z Reset X XX L X High-Z High-Z High-Z Sector Protect (Note 2) L HL Sector Address, VID A6 = L, A1 = H, DIN A0 = L X X Sector Unprotect (Note 2) L HL Sector Address, VID A6 = H, A1 = H, DIN A0 = L X X Temporary Sector Unprotect X XX VID AIN DIN DIN High-Z Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 10 ± 1.0 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A17:A0 in word mode (BYTE# = VIH), A17:A-1 in byte mode (BYTE# = VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Protection/Unprotection” section. Word/Byte Configuration The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configu- ration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address func- tion. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the out- put control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin deter- mines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware re- set. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See Reading Array Data‚ on page 14 for more infor- mation. Refer to the AC Read Operations table for timing specifications and to Figure 14‚ on page 28 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. March 3, 2005 9 11 Page

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