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PDF AM29PDL128G Data sheet ( Hoja de datos )
| Número de pieza | AM29PDL128G | |
| Descripción | Simultaneous Read/ Write Flash Memory | |
| Fabricantes | AMD | |
| Logotipo |  |
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AmPDL128G
Data Sheet
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Publication Number 25685 Revision B Amendment +2 Issue Date July 29, 2002
1 page  
PRELIMINARY
Hardware Reset (RESET#) .................................................... 54
Figure 13. Reset Timings ................................................................ 54
Word/Double Word Configuration (WORD#) .......................... 55
Figure 14. WORD# Timings for Read Operations........................... 55
Figure 15. WORD# Timings for Write Operations........................... 55
Erase and Program Operations .............................................. 56
Figure 16. Program Operation Timings........................................... 57
Figure 17. Accelerated Program Timing Diagram........................... 57
Figure 18. Chip/Sector Erase Operation Timings ........................... 58
Figure 19. Back-to-back Read/Write Cycle Timings ....................... 59
Figure 20. Data# Polling Timings (During Embedded Algorithms).. 59
Figure 21. Toggle Bit Timings (During Embedded Algorithms)....... 60
Figure 22. DQ2 vs. DQ6.................................................................. 60
Temporary Sector Unprotect .................................................. 61
Figure 23. Temporary Sector Unprotect Timing Diagram ............... 61
Figure 24. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 62
Alternate CE# Controlled Erase and Program Operations ..... 63
Figure 25. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 64
Erase And Programming Performance. . . . . . . . 65
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 65
TSOP Pin and BGA Package Capacitance . . . . . 65
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 67
LAB080—80-Ball Fortified Ball Grid Array
10 x 15 mm package .............................................................. 67
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 68
4
Am29PDL128G
July 29, 2002
5 Page 
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29PDL128G Device Bus Operations
Operation
Read
Write
Standby
Output Disable
Reset
Temporary Sector
Unprotect (High Voltage)
CE# OE# WE# RESET#
L LH
H
L HL
H
VCC ±
0.3 V
X
X
VCC ±
0.3 V
L HH
H
X XX
L
X XX
VID
WP#
X
X
X
X
X
X
DQ31–DQ16
Addresses
(Note 1)
AIN
AIN
WORD#
= VIH
DOUT
DIN
WORD#
= VIL
DQ15–
DQ0
DQ30–DQ16 =
High-Z, DQ31 = A-1
DOUT
DIN
X High-Z
High-Z
High-Z
X High-Z
X High-Z
High-Z
High-Z
High-Z
High-Z
AIN DIN
X DIN
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A21–A0 in double word mode (WORD# = VIH), A21–A-1 in word mode (WORD# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection” section.
Word/Double Word Configuration
The WORD# pin controls whether the device data I/O
pins operate in the word or double word configuration.
If the WORD# pin is set at VIH, the device is in double
word configuration, DQ31–DQ0 are active and con-
trolled by CE# and OE#.
If the WORD# pin is set at VIL, the device is in word
configuration, and only data I/O pins DQ15–DQ0 are
active and controlled by CE# and OE#. The data I/O
pins DQ30–DQ16 are tri-stated, and the DQ31 pin is
used as an input for the least significant address bit
(LSB) function, which is named A-1.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH. The WORD# pin determines
whether the device outputs array data in words or dou-
ble words.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Refer to the AC Read-Only Operations table for timing
specifications and to Figure 11 for the timing diagram.
ICC1 in the DC Characteristics table represents the ac-
tive current specification for reading array data.
Random Read (Non-Page Read)
Address access time (tACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (tCE) is the delay from the stable ad-
dresses and stable CE# to valid data at the output in-
puts. The output enable access time is the delay from
the falling edge of the OE# to valid data at the output
10
Am29PDL128G
July 29, 2002
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AM29PDL128G.PDF ] | |
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