PDF T48C893 Data sheet ( Hoja de datos )

Número de pieza	T48C893
Descripción	The multiple times programmable (MTP) version
Fabricantes	ATMEL Corporation
Logotipo
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No Preview Available ! www.DataSheet4U.com T48C893 Flash Version for M44C090/890 and M44C092/892 The T48C893 is the multiple times programmable (MTP) version for the MARC4 ROM types M44C090/890, M44C092/892. The MTP is designed with EEPROM cells so it can be programmed several times. To offer full compati- bility with each ROM version, the I/O configuration is stored into a separate internal EEPROM block during programming.The configuration is download to the I/Os with every power-on reset.. Features / Benefits D 4-Kbyte EEPROM program memory D Wide supply voltage range (1.8 to 6.5 V) D EEPROM programmable options D Read protection for the EEPROM program memory D 16 bidirectional I/Os D Up to 7 external / internal interrupt sources D 8 hardware and software interrupt priorities D Very low sleep current (< 1 µA) D 2 512 bit EEPROM data memory D 256 4 bit RAM data memory D Synchronous serial interface (2-wire, I2C, 3-wire) D Multifunction timer/counter with prescaler/interval timer D Programmable system-clock with prescaler and five different clock sources D Watchdog, POR and brown-out function D Voltage monitoring incl. Lo_BAT detect D Multi-chip link for U3280M VSS VDD OSC1 OSC2 BP10 BP13 BP20/NTE BP21 BP22 BP23 Brown-out protect. RESET Voltage monitor External input VMI Port 1 RC Crystal External oscillators oscillators clock input Clock management EEPROM RAM 4 K x 8 bit 256 x 4 bit MARC4 4-bit CPU core I/O bus UTCM Timer 1 interval- and watchdog timer Timer 2 8/12-bit timer with modulator SSI Serial interface T2I T2O SD SC Timer 3 8-bit timer / counter with modulator and demodulator T3O T3I Data direction + alternate function Port 4 Data direction + interrupt control Port 5 Data dir. + alt. function Port 6 EEPROM 2 32 16 bit BP40 BP42 BP50 BP52 INT3 T2O BP43 INT6 INT1 SC BP41 INT3 BP51 BP53 VMI SD INT6 INT1 T2I BP60 T3O BP63 T3I Figure 1. Block diagram T48C893 Rev. A4, 22-Jan-02 1 (82) 1 page T48C893 Table of Contents (continued) 8-bit Pseudo I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modulation and Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal 2-Wire Multi-Chip Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Control Register 1 (SIC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Control Register 2 (SIC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface Status and Control Register (SISC) . . . . . . . . . . . . . . . . . . . . . . . Serial Transmit Buffer (STB) – Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Receive Buffer (SRB) – Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 Combination Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Combination Mode Timer 2 and SSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Combination Mode Timer 3 and SSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Combination Mode Timer 2 and Timer 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Combination Mode Timer 2, Timer 3 and SSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM – Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization the Serial Interface to the EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 DC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Selectable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 57 59 59 59 60 60 60 61 61 62 62 62 65 68 70 72 73 73 74 74 74 75 75 76 76 76 78 80 81 Rev. A4, 22-Jan-02 5 (82) 5 Page 3.2.4 AÏÏLUÏÏSPÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏTRTTTOOOOASSSSÏÏÏÏÏÏÏÏÏM––––1234ÏÏÏÏÏÏÏÏÏÏÏÏCÏÏÏÏÏCRÏÏÏÏÏÏÏÏÏÏÏÏÏÏAÏÏÏÏÏÏÏÏÏLUÏÏÏÏÏÏÏÏÏTÏÏÏÏÏÏÏÏÏOSÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ Figure 7. ALU zero-address operations T48C893 94 8977 The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two elements of the expression stack (TOS and TOS–1) and returns the result to the TOS. The ALU operations affect the carry/borrow and branch flag in the condition code register (CCR). 3.2.5 I/O Bus The I/O ports and the registers of the peripheral modules are I/O mapped. All communication between the core and the on-chip peripherals takes place via the I/O bus and the associated I/O control. With the MARC4 IN and OUT instructions the I/O bus allows a direct read or write access to one of the 16 primary I/O addresses. More about the I/O access to the on-chip peripherals is described in the section ”Peripheral Modules”. The I/O bus is internal and is not accessible by the customer on the final micro- controller device, but it is used as the interface for the MARC4 emulation (see also the section ”Emulation”). 3.2.6 Instruction Set The MARC4 instruction set is optimized for the high level programming language qFORTH. Many MARC4 instructions are qFORTH words. This enables the compiler to generate a fast and compact program code. The CPU has an instruction pipeline allowing the controller to prefetch an instruction from program memory at the same time as the present instruction is being executed. The MARC4 is a zero address machine, the instructions containing only the operation to be performed and no source or destination address fields. The operations are implicitly performed on the data placed on the stack. There are one and two byte instructions which are executed within 1 to 4 machine cycles. A MARC4 machine cycle is made up of two system clock cycles (SYSCL). Most of the instructions are only one byte long and are executed in a single machine cycle. For more information refer to the ”MARC4 Programmer’s Guide”. 3.2.7 Interrupt Structure The MARC4 can handle interrupts with eight different priority levels. They can be generated from the internal and external interrupt sources or by a software interrupt from the CPU itself. Each interrupt level has a hard-wired priority and an associated vector for the service routine in the program memory (see table 2). The programmer can postpone the processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt occurrence will still be registered, but the interrupt routine only started after the I flag is set. All interrupts can be masked, and the priority individually software configured by programming the appropriate control register of the interrupting module. (see section ”Peripheral Modules”). Rev. A4, 22-Jan-02 11 (82) 11 Page

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