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PDF T48C510 Data sheet ( Hoja de datos )
| Número de pieza | T48C510 | |
| Descripción | 4-bit MTP Universal Microcontroller | |
| Fabricantes | ATMEL Corporation | |
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T48C510
MARC4 – 4-bit MTP Universal Microcontroller
The T48C510 is an Multi Time Programmable (MTP) microcontroller which is pin and functionally compatible to the
Atmel Wireless & Microcontrollers’ M44C510E mask programmable microcontroller. It contains EEPROM, RAM,
up to 34 digital I/O pins, up to 10 maskable external interrupt sources, 4 maskable internal interrupts, a watchdog timer,
interval timer, 2 x 8-bit multifunction timer/counter module and a versatile software configurable on-chip system clock
module.
Features / Benefits
D Programmable system clock with prescaler and five
different clock sources:
– Up to 8-MHz crystal oscillator (system clock)
– 32-kHz crystal oscillator
– RC-oscillator fully integrated
– RC-oscillator with external resistor adjustment
– External clock input
D Wide supply-voltage range (2.4 V to 6.2 V)
D Very low halt current
D 4 KByte program EEPROM, 256 x 4-bit RAM
D I/O ports – bitwise configurable with combined inter-
rupt handling (for serial I/O applications)
D 2 x 8-bit multifunction timer/counters
D Coded reset and watchdog timer
D Power-on reset and “brown out” function
D Various power-down modes
D Efficient, hardware-controlled interrupt handling
D High-level programming language in qFORTH
D 8 hard- and software interrupt priority levels
D Comprehensive library of useful routines
D Up to 10 external and 4 internal interrupts, bitwise D Windows 95/NT based development and programmer
maskable with programmable priority level
tools
D Up to 34 I/O lines
TE SCLIN OSCIN OSCOUT AVDD VSS NRST VDD TIM1
Config.
EEPROM
Test System Real time
Sleep clock
clock
Master
reset
EEPROM RAM
4K x 8 bit 256 x 4 bit
MARC4
4-bit CPU core
Watch–
dog
Prescaler
I/O bus
Timer/
counter
Timer 1
Timer 0
Melody
& buzzer
I/O I/O I/O
I/O
I/O I/O
I/O
I/O
I/O
Interrupt
& reset
Interrupt
Interrupt
44 44
4
PM Port 0 Port 1 Port 5 Port 7 Port A
4
Port B
42
Port C Port 6
4
Port 4
Figure 1. Block diagram
16536
Rev. A2, 26-Feb-01
Preliminary Information
1 (61)
1 page  
T48C510
1 MARC4 Architecture
SRcyleossCtcSeeRlkltomeeceskpeÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏt ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏPmÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏreoÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏIcmIgndnosretÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏnoItaecrntrrmurosryoÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏcdutblrtepluuiIeortÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ/scrOntioÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏbMnusÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏAPCÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏRMCeÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏm4oÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏrCCyÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏCbORSXYuRPPÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏsREÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏTOÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏSAÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏL2R5UÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ6AxÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ4M-bÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏit ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
On–chip peripheral modules
Figure 3. MARC4 core
94 8973
1.1 General Description
The functionality, programming and pinning of the
T48C510 is compatible with the M44C510E mask pro-
grammable microcontroller from Atmel Wireless &
Microcontrollers. All on-chip modules are addressed and
controlled with exactly the same programming code, so
that a program targeted for the M44C510E can be read
directly into the T48C510 and will operate in the same
fashion.
The MARC4 microcontroller consists of an advanced
stack based 4-bit CPU core and on-chip peripherals. The
CPU is based on the HARVARD architecture with physi-
cally separate program memory (EEPROM) and data
memory (RAM). Three independent buses, the instruc-
tion bus, the memory bus and the I/O bus are used for
parallel communication between EEPROM, RAM and
peripherals. This enhances program execution speed by
allowing both instruction prefetching, and a simultaneous
communication to the on-chip peripheral circuitry. The
extremely powerful integrated interrupt controller with
associated eight prioritized interrupt levels supports fast
and efficient processing of hardware events. The MARC4
is designed for the high-level programming language
qFORTH. The core includes an expression and a return
stack. This architecture allows high-level language pro-
gramming without any loss in efficiency or code density.
1.2 Components of MARC4 Core
The core contains EEPROM, RAM, ALU, a program
counter, RAM address registers, an instruction decoder
and an interrupt controller. The following sections de-
scribe each functional block in more detail:
1.2.1 EEPROM
The program memory (EEPROM) is programmed with
the customer application program. The EEPROM is ad-
dressed by a 12-bit wide program counter, thus
predefining a maximum program bank size of 4 Kbytes.
Rev. A2, 26-Feb-01
Preliminary Information
5 (61)
5 Page 
T48C510
Table 2 Interrupt priority table
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁInIIIIIIIItNNNNNNNNeÁÁÁÁÁÁÁÁÁrTTTTTTTTru01234567pÁÁÁÁÁÁÁÁÁt ÁÁÁÁÁÁÁÁÁPhloriÁÁÁÁÁÁÁÁÁgiw↓oh|||||reeisÁÁÁÁÁÁÁÁÁtstyt ÁÁÁÁÁÁÁÁÁEEÁÁÁÁÁÁÁÁÁPRÁÁÁÁÁÁÁÁÁO01100111MCCE48048ÁÁÁÁÁÁÁÁÁ00000000hhhhhAhhhdÁÁÁÁÁÁÁÁÁdreÁÁÁÁÁÁÁÁÁss ÁÁÁÁÁÁÁÁÁMaÁÁÁÁÁÁÁÁÁYYYYYYYYskeeeeeeeeassssssssÁÁÁÁÁÁÁÁÁble ÁÁÁÁÁÁÁÁÁCDDEEFFF08C88808ÁÁÁÁÁÁÁÁÁhhhhhhhh((((((((SSSSÁÁÁÁÁÁÁÁÁSSSSCCCCCCCCAAAAAAAAÁÁÁÁÁÁÁÁÁLLLLLLLLLLLLLLLLÁÁÁÁÁÁÁÁÁ111100018C0448CE000000ÁÁÁÁÁÁÁÁÁ00hhhhhhhhI)))))))n)ÁÁÁÁÁÁÁÁÁterruÁÁÁÁÁÁÁÁÁpt OÁÁÁÁÁÁÁÁÁpcÁÁÁÁÁÁÁÁÁodeÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
1.3.1 Hardware Interrupts
Table 3 Hardware interrupts
Interrupt
Source
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁNRST external
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁWatchdog
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁPort A coded reset
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁPort A monitor
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁPort B monitor
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁPort 60 external
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁPort 61 external
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁInterval timer INTA
Possible Interrupt Priorities
01234567
****
****
****
****
**
RST
X
#
#
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁInterval timer INTB
*
*
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁTimer 0
****
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁTimer 1
****
Interrupt Mask
Register Bit
––
––
––
PAIPR
3
PBIPR
3
P6CR
1,0
P6CR
3,2
ITIPR
0
ITIPR
1
T0CR
0
T1CR
0
Function
low level active
1/2 – 2 sec. time out
level any inputs
any edge, any input
any edge, any input
any edge
any edge
1 of 8 frequencies
(1 – 128 Hz)
1 of 8 frequencies
(8 – 8192 Hz)
overflow/compare/
end measurement
compare
X = hardwired (neither optional or software configurable)
# = configurable option (see “Hardware Options”)
* = software configurable (see “Peripheral Modules” section for further details)
In the T48C510, there are eleven hardware interrupt
sources which can be programmed to occupy a variety of
priority levels. With the exception of the reset sources
(RST), each source can be individually masked by mask
bits in the corresponding control registers. An overview
of the possible hardware configurations is shown in
table 3.
The software triggered interrupt operates in exactly the
same way as any hardware triggered interrupt.
The SWI instruction takes the top two elements from the
expression stack and writes the corresponding bits via the
I/O bus to the interrupt pending register. Thus, by using
the SWI instruction, interrupts can be re-prioritized or
lower priority processes scheduled for later execution.
1.3.2 Software Interrupts
The program can generate interrupts using the software
interrupt instruction (SWI) which is supported in
qFORTH by predefined macros named SWI0...SWI7.
Rev. A2, 26-Feb-01
Preliminary Information
11 (61)
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet T48C510.PDF ] | |
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