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PDF PI74FCT162244MT Data sheet ( Hoja de datos )

Número de pieza PI74FCT162244MT
Descripción Fast CMOS 16-Bit Heavy Buffer/Line Drivers
Fabricantes Pericom Semiconductor 
Logotipo Pericom Semiconductor Logotipo



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PI74FCT162244MT
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PI74FCT162244MT
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Fast CMOS 16-Bit
Heavy Buffer/Line Drivers
Product Features:
• Very high-speed buffer drivers for 150 pF heavy load
and all 16-bit switching in 4.8ns max
• Meets JEDEC specification for DRAM DIMM module
buffer propagation delay
• Low noise drivers: minimal undershoot/ringback and
typical VOLP (output ground bounce) < 0.6V
• Packages available:
– 48-pin 240-mil wide plastic TSSOP (A)
– 48-pin 300-mil wide plastic SSOP (V)
Logic Block Diagram
Product Description:
Pericom Semiconductor’s PI74FCT series of logic circuits are
produced in the Company’s advanced CMOS technology,
achieving industry leading speed grades.
The PI74FCT162244MT is a non-inverting 16-bit buffer/line
driver designed specifically for applications driving heavy
loads—ideally for DRAM modules/arrays and heavy load bus
applications. This very high-speed, high-drive, low noise buffer
driver device meets the JEDEC specification for DRAM DIMM
module buffer drivers.
The PI74FCT162244MT offers a flow-through organization for
ease of board layout. This part is plug-in compatible with the
74ABT16244/162244 and excels in applications where much
higher speed and lower power dissipation are required.
The output drivers of the PI74FCT162244MT have the features
of a balanced drive and controlled edge rate, resulting in
minimal undershoot/ringback and ground bounce. This
eliminates the need for external series termination resistors.
1OE
1A0
3OE
1Y0 3A0
3Y0
1A1 1Y1 3A1 3Y1
1A2 1Y2 3A2 3Y2
1A3 1Y3 3A3 3Y3
2OE
2A0
2A1
2A2
2A3
4OE
2Y0 4A0
2Y1 4A1
2Y2 4A2
2Y3 4A3
4Y0
4Y1
4Y2
4Y3
1 PS2043A 03/12/96

1 page




PI74FCT162244MT pdf
PI74FCT162244MT
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Switching Characteristics over Operating Range - High-LoadCondition
Parameters Description
tPLH Propagation Delay(2)
tPHL XAX to XYX
tPZH Output Enable Time
tPZL XOE to XAX or XYX
Conditions(1)
162244MT
Com.
Min Max Unit
CL = 150 pF
1.5 4.8 ns
All 16 Bits Switching
CL = 50 pF
RL = 500
1.5 6.2 ns
tPHZ Output Disable Time(3)
tPLZ XOE to XAX or XYX
1.5 5.6 ns
tSK(o) Output Skew(4)
— 0.5 ns
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same
direction. This parameter is guaranteed by design.
5 PS2043A 03/12/96

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