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PDF CY7C1464AV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1464AV33 | |
| Descripción | (CY7C146xAV33) 36-Mbit Pipelined SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
SRAM with NoBL™ Architecture
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate the
need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 3.3V power supply
• 3.3V/2.5V I/O power supply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 3.2 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• CY7C1460AV33 and CY7C1462AV33 are available in
lead-free 100-pin TQFP and 165-Ball fBGA packages;
CY7C1464AV33 available in 209-Ball fBGA package
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V,
1 Mbit x 36 / 2 Mbit x 18 / 512K x72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They
are designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1460AV33/
CY7C1462AV33/CY7C1464AV33 are equipped with the
advanced (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent Write/Read transitions.The
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are pin
compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock input
is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the Byte Write Selects
(BWa–BWh for CY7C1464AV33, BWa–BWd for CY7C1460AV33
and BWa–BWb for CY7C1462AV33) and a Write Enable (WE)
input. All writes are conducted with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
Logic Block Diagram-CY7C1460AV33 (1 Mbit x 36)
A0, A1, A
MODE
CLK C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
BWb
BWc
BWd
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQs
DQPa
DQPb
DQPc
DQPd
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05353 Rev. *A
Revised November 19, 2004
1 page  
PRELIMINARY
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Pin Configurations (continued)
209-Ball PBGA
CY7C1464AV33 (512K x 72)
1234567
A DQg
DQg
A
CE2 A ADV/LD A
B DQg DQg BWSc BWSg NC
WE
A
C DQg DQg BWSh BWSd NC CE1
NC
D DQg DQg VSS NC NC OE
NC
E DQPg DQPc VDDQ VDDQ VDD
VDD
VDD
F
DQc
DQc
VSS
VSS
VSS NC
VSS
G
DQc
DQc
VDDQ VDDQ
VDD
NC
VDD
H
DQc
DQc
VSS
VSS
VSS NC
VSS
J
DQc
DQc
VDDQ VDDQ
VDD
NC
VDD
K NC NC CLK NC VSS CEN VSS
L
DQh
DQh VDDQ
VDDQ
VDD
NC
VDD
M
DQh
DQh VSS
VSS
VSS NC
VSS
N
DQh
DQh VDDQ
VDDQ
VDD
NC
VDD
P
DQh DQh VSS
VSS
VSS ZZ
VSS
R
DQPd DQPh VDDQ VDDQ
VDD
VDD
VDD
T
DQd DQd VSS
NC
NC MODE NC
U DQd DQd NC A NC/72M A
A
V
DQd DQd
A
A
A A1 A
W
DQd DQd TMS
TDI
A
A0 A
8 9 10 11
CE3
BWSb
BWSe
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
VDDQ
VSS
VDDQ
VSS
VDDQ
NC
A
A
TDO
A DQb
BWSf DQb
BWSa DQb
VSS
VDDQ
VSS
DQb
DQPf
DQf
VDDQ
VSS
DQf
DQf
VDDQ
DQf
NC NC
VDDQ
VSS
VDDQ
DQa
DQa
DQa
VSS
VDDQ
VSS
NC
A
TCK
DQa
DQPa
DQe
DQe
DQe
DQe
DQb
DQb
DQb
DQb
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
Pin Definitions
Pin Name
A0
A1
A
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
WE
ADV/LD
I/O Type
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Pin Description
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,
BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf
controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
Document #: 38-05353 Rev. *A
Page 5 of 27
5 Page 
PRELIMINARY
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 incor-
porates a serial boundary scan test access port (TAP). This
part is fully compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic level.
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
TAP Controller State Diagram
1 TEST-LOGIC
RESET
0
0 RUN-TEST/ 1
IDLE
SELECT
DR-SCAN
1
0
1
CAPTURE-DR
0
SHIFT-DR 0
1
EXIT1-DR
1
0
PAUSE-DR 0
1
0
EXIT2-DR
1
UPDATE-DR
10
SELECT
IR-SCAN
1
0
1
CAPTURE-IR
0
SHIFT-IR
0
1
EXIT1-IR
1
0
PAUSE-IR 0
1
0
EXIT2-IR
1
UPDATE-IR
10
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0
Bypass Register
Selection
TDI Circuitry
210
Instruction Register
31 30 29 . . . 2 1 0
Selection
Circuitry
Identification Register
x . . . . . 210
Boundary Scan Register
TDO
TCK
TMS TAP CONTROLLER
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
Document #: 38-05353 Rev. *A
Page 11 of 27
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet CY7C1464AV33.PDF ] | |
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