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PDF CY7C1302DV25 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1302DV25 | |
| Descripción | 9-Mbit Burst of Two Pipelined SRAMs | |
| Fabricantes | Cypress Semiconductor | |
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PREMILINARY
CY7C1302DV25
9-Mbit Burst of Two Pipelined SRAMs
with QDR™ Architecture
Features
• Separate independent Read and Write data ports
— Supports concurrent transactions
• 167-MHz clock for high bandwidth
— 2.5 ns clock-to-Valid access time
• 2-word burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 333 MHz) @ 167 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
and flight time mismatching
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball
(11 x 15 matrix)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG Interface
Configurations
CY7C1302DV25 – 512K x 18
Functional Description
The CY7C1302DV25 is a 2.5V Synchronous Pipelined SRAM
equipped with QDR™ architecture. QDR architecture consists
of two separate ports to access the memory array. The Read
port has dedicated data outputs to support Read operations
and the Write Port has dedicated data inputs to support Write
operations. Access to each port is accomplished through a
common address bus. The Read address is latched on the
rising edge of the K clock and the Write address is latched on
the rising edge of K clock. QDR has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus required with common I/O devices. Accesses to
the CY7C1302DV25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock
(K). In order to maximize data throughput, both Read and
Write ports are equipped with DDR interfaces. Therefore, data
can be transferred into the device on every rising edge of both
input clocks (K and K) and out of the device on every rising
edge of the output clock (C and C, or K and K in a single clock
domain) thereby maximizing performance while simplifying
system design. Each address location is associated with two
18-bit words that burst sequentially into or out of the device.
Depth expansion is accomplished with a Port Select input for
each port. Each Port Select allows each port to operate
independently. 38-05625
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Logic Block Diagram (CY7C1302DV25)
D[17:0]
18
A(17:0)
18
K
K
Address
Register
CLK
Gen.
Write
Data Reg
Write
Data Reg
256Kx18 256Kx18
Memory Memory
Array Array
Read Data Reg.
Address
Register
18 A(17:0)
Control
Logic
RPS
C
C
Vref
WPS
BWS0
BWS1
Control
Logic
36 18
Reg. Reg. 18
18
Reg.
18
18
Q[17:0]
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05625 Rev. **
Revised July 29, 2004
1 page  
PREMILINARY
CY7C1302DV25
Truth Table[2, 3, 4, 5, 6, 7]
Operation
Write Cycle:
Load address on the rising edge of K clock; input write
data on K and K rising edges.
Read Cycle:
Load address on the rising edge of K clock; wait one
cycle; read data on 2 consecutive C and C rising edges.
NOP: No Operation
K
L-H
L-H
L-H
Standby: Clock Stopped
Stopped
Write Cycle Descriptions[2,8]
RPS
X
L
H
X
WPS
L
X
H
X
DQ
D(A+0)at
K(t) ↑
DQ
D(A+1) at
K(t) ↑
Q(A+0) at Q(A+1) at
C(t+1)↑
C(t+1) ↑
D=X
Q = High-Z
Previous
State
D=X
Q = High-Z
Previous
State
BWS0
L
L
L
BWS1
L
L
H
K
L-H
–
L-H
L H–
H L L-H
H L–
H H L-H
K Comments
– During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.
L-H During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.
– During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the
device. D[17:9] remains unaltered.
L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the
device. D[17:9] remains unaltered.
– During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device.
D[8:0] remains unaltered.
L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device.
D[8:0] remains unaltered.
– No data is written into the device during this portion of a Write operation.
H H – L-H No data is written into the device during this portion of a Write operation.
Notes:
2. X = Don't Care, H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically. 38-05625
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0, BWS1 can be altered on different portions of a Write cycle, as long
as the set-up and hold requirements are achieved. 38-05625
Document #: 38-05625 Rev. **
Page 5 of 18
5 Page 
PREMILINARY
CY7C1302DV25
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST Output Bus Three-state
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a three-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus three-state”,
is latched into the preload register during the “Update-DR”
state in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05625 Rev. **
Page 11 of 18
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