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PDF LMK03000C Data sheet ( Hoja de datos )

Número de pieza LMK03000C
Descripción (LMK03000 / LMK03001) Precision Clock Conditioner
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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ADVANCE INFORMATION
November 2006
LMK03000/LMK03000C/LMK03001/LMK03001C
Precision Clock Conditioner with Integrated VCO
General Description
The LMK03000/LMK03000C/LMK03001/LMK03001C preci-
sion clock conditioners combine the functions of jitter clean-
ing/reconditioning, multiplication, and distribution of a refer-
ence clock. The devices integrate a Voltage Controlled
Oscillator (VCO), a high performance Integer-N Phase
Locked Loop (PLL), a partially integrated loop filter, three
LVDS, and five LVPECL clock output distribution blocks.
The VCO output is optionally accessible on the Fout port. In-
ternally, the VCO output goes through an Input Divider to feed
the various clock distribution blocks.
Each clock distribution block includes a programmable di-
vider, a phase synchronization circuit, a programmable delay,
a clock output mux, and an LVDS or LVPECL output buffer.
This allows multiple integer-related and phase-adjusted
copies of the reference to be distributed to eight system com-
ponents.
The clock conditioners come in a 48-pin LLP package and are
footprint compatible with other clocking devices in the same
family.
Features
Integrated VCO and Integer-N PLL
Two performance grades (12 kHz to 20 MHz)
LMK03000/LMK03001: Less than 800 fs RMS
LMK03000C/LMK03001C: Less than 400 fs RMS
Two VCO frequency plans
LMK03000/LMK03000C: 1185 to 1296 MHz
LMK03001/LMK03001C: 1470 to 1570 MHz
Clock output frequency range of 1 to 785 MHz
3 LVDS and 5 LVPECL clock outputs
Partially integrated loop filter
Dedicated divider and delay blocks on each clock output
Pin compatible family of clocking devices
3.15 to 3.45 V operation
Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
Target Applications
Data Converter Clocking
SONET/SDH, DSLAM
Networking
Wireless Infrastructure
Medical
Test and Measurement
Military / Aerospace
Functional Block Diagram
© 2006 National Semiconductor Corporation 202114
20211401
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LMK03000C pdf
Symbol
JitterADD
tSKEW
VOD
ΔVOD
VOS
ΔVOS
ISA
ISB
ISAB
JitterADD
tSKEW
VOH
VOL
VOD
VIH
VIL
IIH
IIL
VOH
VOL
VIH
VIL
IIH
IIL
Parameter
Conditions
Min Typ
Clock Distribution Section (Note 8) - LVDS Clock Outputs (CLKout0 to CLKout2)
Additive RMS Jitter (Note 8)
CLKoutX_MUX
RL = 100 Ω
= Bypass
Input Bus = 785
MHz
Bandwidth = 12 kHz
to 20 MHz
CLKoutX_MUX
= Divided
CLKoutX_DIV =
4
40
150
CLKoutX to CLKoutY
Differential Output Voltage
Change in magnitude of VOD for
complementary output states
Equal loading and identical channel
configuration
RL = 100 Ω
RL = 100 Ω
RL = 100 Ω
-30 ±4
250 350
-35
Output Offset Voltage
Change in magnitude of VOS for
complementary output states
RL = 100 Ω
RL = 100 Ω
1.125
-35
1.25
Clock Output Short Circuit Current
single ended
Single ended outputs shorted to GND -24
Clock Output Short Circuit Current
differential
Complementary outputs tied together -12
Clock Distribution Section (Note 8) - LVPECL Clock Outputs (CLKout3 to CLKout7)
Additive RMS Jitter (Note 8)
RL = 100 Ω
Input Bus = 785
CLKoutX_MUX
= Bypass
MHz
CLKoutX_MUX
Integration
= Divided
Bandwidth = 12 kHz CLKoutX_DIV =
to 20 MHz
4
40
150
CLKoutX to CLKoutY
Equal loading and identical channel
configuration
-30 ±3
Termination = 50 Ω to Vcc - 2 V
Output High Voltage
Vcc -
0.98
Output Low Voltage
Termination = 50 Ω to Vcc - 2 V
Vcc -
1.8
Differential Output Voltage
660 810
Digital LVTTL Interfaces (Note 9)
High-Level Input Voltage
2.0
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
High-Level Output Voltage
VIH = Vcc
VIL = 0
IOH = -500 µA
-1.0
-1.0
Vcc -
0.4
Low-Level Output Voltage
IOL = -500 µA
Digital MICROWIRE Interfaces (Note 10)
High-Level Input Voltage
1.6
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
VIH = Vcc
VIL = 0
-1.0
-1.0
Max
30
450
35
1.375
35
24
12
30
965
Vcc
0.8
1.0
1.0
0.4
Vcc
0.4
1.0
1.0
Units
fs
ps
mV
mV
V
mV
mA
mA
fs
ps
V
V
mV
V
V
µA
µA
V
V
V
V
µA
µA
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