PDF ADCMP600 Data sheet ( Hoja de datos )

Número de pieza ADCMP600
Descripción (ADCMP600 - ADCMP602) Single-Supply TTL/CMOS Comparator
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No Preview Available ! ADCMP600 Hoja de datos, Descripción, Manual
Preliminary Technical Data
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,
Single-Supply TTL/CMOS Comparators
10 mV sensitivity rail to rail at VCC = 2.5 V
Input common-mode voltage from −0.2 V to VCC + 0.2 V
Low glitch CMOS-/TTL-compatible output stage
3 ns propagation delay
15 mW at 3.3 V
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection > 60 dB
Improved replacement for MAX999
−40°C to +125°C operation
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)
The ADCMP600, ADCMP601, and ADCMP602 are very fast
comparators fabricated on Analog Devices’ proprietary XFCB2
process. These comparators are exceptionally versatile and easy
to use. Features include an input range from VEE − 0.5 V to VCC +
0.5 V, low noise TTL-/CMOS-compatible output drivers, and
latch inputs with adjustable hysteresis and/or shutdown inputs.
The devices offer 3 ns propagation delay with 5 mV overdrive
on 4 mA typical supply current.
A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a −0.5 V to +3.0 V
input signal range up to a +5.5 V positive supply with a −0.5 V
to +6 V input signal range. Split input/output supplies with no
sequencing restrictions on the ADCMP602 support a wide
(Except ADCMP600)
(ADCMP602 Only)
Figure 1.
input signal range while still allowing independent output
swing control and power savings.
The TTL-/CMOS-compatible output stage is designed to drive
up to 5 pF with full timing specs and to degrade in a graceful
and linear fashion as additional capacitance is added. The
comparator input stage offers robust protection against large
input overdrive, and the outputs do not phase reverse when the
valid input signal range is exceeded. High speed latch and
programmable hysteresis features are also provided with a
unique single-pin control option.
The ADCMP600 is available in both 5-lead SC70 and SOT-23
packages, the ADCMP601 is available in a 6-lead SC70 package,
and the ADCMP602 is available in 8-lead MSOP and LSCFP
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.

1 page

ADCMP600 pdf
Preliminary Technical Data
Table 2.
Supply Voltages
Input Supply Voltage (VCCI to GND)
Output Supply Voltage
Positive Supply Differential
Input Voltages
Input Voltage
Differential Input Voltage
Maximum Input/Output Current
Shutdown Control Pin
Applied Voltage (HYS to GND)
Maximum Input/Output Current
Latch/Hysteresis Control Pin
Applied Voltage (HYS to GND)
Maximum Input/Output Current
Output Current
Operating Temperature, Ambient
Operating Temperature, Junction
Storage Temperature Range
−0.5 V to +6.0 V
−0.5 V to +6.0 V
−6.0 V to +6.0 V
−0.5 V to VCCI + 0.5 V
±(VCCI + 0.5 V)
±50 mA
−0.5 V to VCCO + 0.5 V
±50 mA
−0.5 V to VCCO + 0.5 V
±50 mA
±50 mA
−40°C to +125°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
JA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
ADCMP600 SC70 5-lead
ADCMP600 SOT-23 5-lead
ADCMP601 SC70 6-lead
ADCMP602 MSOP 5-lead
θJA1 Unit
426 °C/W
302 °C/W
426 °C/W
130 °C/W
1 Measurement in still air.
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrA | Page 5 of 16

5 Page

ADCMP600 arduino
Preliminary Technical Data
Leaving the LE/HYS pin disconnected results in a fixed hysteresis
of 2 mV; driving this pin high removes the hysteresis. The max-
imum hysteresis that can be applied using this pin is approximately
160 mV. Figure 18 illustrates the amount of hysteresis applied as
a function of the external resistor value, and Figure TBD illustrates
hysteresis as a function of the current.
The hysteresis control pin appears as a 1.25 V bias voltage seen
through a series resistance of 7k ± 20% throughout the hysteresis
control range. The advantages of applying hysteresis in this manner
are improved accuracy, improved stability, reduced component
count, and maximum versatility. An external bypass capacitor is
not recommended on the HYS pin because it impairs the latch
function and often degrades the jitter performance of the device.
As described in the Using/Disabling the Latch Feature section,
hysteresis control need not compromise the latch function.
In both op amps and comparators, rail-to-rail inputs of this type
have a dual front-end design. Certain devices are active near the
VCC rail and others are active near the VEE rail. At some predeter-
mined point in the common-mode range, a crossover occurs. At
this point, normally VCC/2, the direction of the bias current reverses
and the measured offset voltages and currents change.
The ADCMP600/ADCMP601/ADCMP602 slightly elaborate
on this scheme. With VCC less than 4 V, this crossover is at the
expected VCC/2, but with VCC greater than 4 V, the crossover point
instead follows VCC 1:1, bringing it to approximately 3 V with VCC at
5 V. This means that when VCC is greater than 4, the comparator
input characteristics more closely resemble those of common
types of inputs that are not rail to rail.
Figure 18. Hysteresis vs. RHYS Control Resistor
(Remove if device is stable.)
As with most high speed comparators without hysteresis, a min-
imum slew rate must be met to ensure that the device does not
oscillate as the input signal crosses the threshold. This oscillation
is due to the high gain bandwidth of the comparator in combi-
nation with feedback parasitics inherent in the package and PC
board. A minimum slew rate of TBD V/μs ensures clean output
transitions from the ADCMP601 or ADCMP602 comparator
without hysteresis. In many applications, chattering is not harmful.
Rev. PrA | Page 11 of 16

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