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PDF MB15E07SL Data sheet ( Hoja de datos )
| Número de pieza | MB15E07SL | |
| Descripción | Single Serial Input PLL Frequency Synthesizer On-Chip 2.5 GHz Prescaler | |
| Fabricantes | Fujitsu Media Devices | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-chip 2.5 GHz Prescaler
MB15E07SL
DS04-21358-3E
s DESCRIPTION
The Fujitsu MB15E07SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2.5 GHz prescaler.
The 2.5 GHz prescaler has a dual modulus division ratio of 32/33 or 64/65 enabling pulse swallowing operation.
The supply voltage range is between 2.4 V and 3.6 V. The MB15E07SL uses the latest BiCMOS process, as a result
the supply current is typically 3.5 mA at 2.7 V. A refined charge pump supplies well-balanced output currents of 1.5
mA and 6 mA. The charge pump current is selectable by serial data.
MB15E07SL is ideally suited for wireless mobile communications, such as GSM (Global System for Mobile
Communications) and PCS.
s FEATURES
• High frequency operation: 2.5 GHz max
• Low power supply voltage: VCC = 2.4 to 3.6 V
• Ultra Low power supply current: ICC = 3.5 mA typ. (VCC = Vp = 2.7 V, Ta = +25°C, in locking state)
ICC = 4.0 mA typ. (VCC = Vp = 3.0 V, Ta = +25°C, in locking state)
• Direct power saving function: Power supply current in power saving mode
Typ. 0.1 µA (VCC = Vp = 3.0 V, Ta = +25°C), Max. 10 µA (VCC = Vp = 3.0 V)
• Dual modulus prescaler: 32/33 or 64/65
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
• Software selectable charge pump current
• On-chip phase control for phase comparator
• Operating temperature: Ta = –40 to +85°C
• Pin compatible with MB15E07, MB15E07L
s PACKAGES
16-pin plastic SSOP
16-pad plastic BCC
(FPT-16P-M05)
(LCC-16P-M06)
1
1 page  
MB15E07SL
s ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input voltage
Output voltage
Storage temperature
Symbol
VCC
VP
VI
VO
VO
Tstg
Condition
–
–
–
Except Do
Do
–
Rating
Min.
Max.
–0.5
4.0
VCC 6.0
–0.5
VCC +0.5
GND
VCC
GND
VP
–55 +125
Unit
V
V
V
V
V
°C
Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter
Power supply voltage
Input voltage
Operating temperature
Symbol
VCC
VP
VI
Ta
Min.
2.4
VCC
GND
–40
Value
Typ.
3.0
–
–
–
Max.
3.6
5.5
VCC
+85
Unit
V
V
V
°C
Remark
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
5 Page 
MB15E07SL
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
* : When the LPF and VCO characteristics are similar to
(1), set FC bit high.
* : When the VCO characteristics are similar to (2), set
FC bit low.
(1)
PLL LPF VCO
VCO
Output
Frequency
LPF Output Voltage
(2)
3. Do Output Control
Table 9. ZC Pin Setting
ZC pin
Do output
H Normal output
L High impedance
4. Power Saving Mode (Intermittent Mode Control Circuit)
Table 10. PS Pin Setting
PS pin
H
L
Status
Normal mode
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the signal PLL, the lock detector, LD, remains high, indicating a locked condition.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because
of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
Note: When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 µs.
11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet MB15E07SL.PDF ] | |
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