|
|
PDF VSC8124 Data sheet ( Hoja de datos )
| Número de pieza | VSC8124 | |
| Descripción | Target Specification | |
| Fabricantes | Vitesse Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de VSC8124 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
VITESSE
SEMICONDUCTOR CORPORATION
Target Specification
VSC8124
2.488 Gb/s Quad
Data Re-timer
Features
• Four Channel 2.488 Gb/s Data Recovery
• SONET Quality Jitter Tolerance
• Fastlock Data Acquisition less than 200
Bit Times
• Loss of Signal Indicators
• Long Strings of Static Data Tolerated by the
Clock Recovery Circuit without Loss of Signal
• First Order Clock Recovery Loop Minimizes
Jitter Accumulation
• Differential on Chip Terminated Serial Data I/O
• Bypass for OC3, OC12 Data Rates
• 155.52 MHz Reference Clock Frequency
• 3.3V Supply Operation
• 14 x 14mm, 100 Pin Thermally Enhanced
TQFP Package
General Description
The VSC8124 is a four channel, 2.5 Gb/s data re-timer for cleaning up data downstream of optical links or
cross point switches. Serial data at the 2.5 Gb/s rate is independently re-timed on four channels, and driven dif-
ferentially by CML drivers. The re-timing function on each channel can be individually bypassed for lower rate
signals or test purposes. The VSC8124 provides four independent loss of signal indicators in the event of loss of
synchronous data transitions.
G52271-0, Rev. 1.14
2/23/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1
1 page  
VITESSE
SEMICONDUCTOR CORPORATION
Target Specification
VSC8124
2.488 Gb/s Quad
Data Re-timer
Figure 3: Fastlock Timing Diagram
Input Data Valid Data
Fastlock
Output Data Valid Data
200 Bit Times
1010...
80 Bit Times
Valid Data
200 Bit Times
Valid Data
Fast Lock
The VSC8124 supports a fastlock clock recovery mode which enables the clock recovery unit to lock the
retiming clock to the incoming data within 80 bit periods of initiation. As a requirement for the operation of the
fastlock function, the driving system must send a 0101 bit pattern while the fastlock pin is at a high logic level.
The FASTLOCK function is active simultaneously on all four data channels The fastlock pin has a TTL input
receiver meeting the specifications contained in Table 7. Note that jitter tolerance and re-timed data jitter are
degraded in FASTLOCK mode.
Loss of Signal
The loss of signal (LOS) circuitry is shared among four serial data channels, sampling the signal condition
on each channel sequentially. There is a loss of signal latch and active low indicator pin (LOS[0:3]N) for each
channel. In addition, there is an alarm pin (LOSALMN) which indicates the OR of the latched states of the four
channel indicators. The alarm pin uses an open drain output, so the alarm pins from multiple parts can be wired
together. A weak external pull resistor (approximately 1k Ohm) must be provided to utilize the wired NOR
alarm function. To facilitate system troubleshooting, the LOS latches can only be cleared by the active high
LOSCLR input.
The loss of signal clear (LOSCLR) input will cause all four loss of signal indicators LOS[0:3]N and the loss
of signal alarm (LOSALM) to be cleared. The LOSCLR input is asynchronous. It must be held active for at
least two reference clock cycles. A channel found to be missing after the error latch has been cleared, will again
set its error latch and the LOSALMN.
The LOS circuit examines a selected clock recovery channel for expected data transition activity. Expected
data activity includes pseudo-random data at a baud rate 16 times the reference clock frequency, and data
including at least 8500 consecutive bits of a 101010... pattern. The detector will allow the OC-48 framing pat-
tern to pass without triggering LOS. The LOS detector is disabled when FASTLOCK mode is active.
To assist diagnostic procedures, the effect of individual loss of signal indicators in the loss of signal alarm
can be masked. This is controlled by the MASK[0:3] pins. Each of those pins, when pulled high, disables the
effect of its respective channel on the loss of signal alarm (LOSALM). If all MASK pins are pulled high, the
LOSALM signal will not pull down. The loss of signal indicators for individual channels are not affected by the
MASK pins.
G52271-0, Rev. 1.14
2/23/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
5 Page 
VITESSE
SEMICONDUCTOR CORPORATION
Target Specification
VSC8124
2.488 Gb/s Quad
Data Re-timer
Absolute Maximum Ratings
Power Supply Voltage, (VCC) ......................................................................................................-0.5 V to +4.0 V
DC Input Voltage (Differential inputs) .................................................................................-0.5 V to VCC + 0.5V
DC Input Voltage (TTL inputs)............................................................................................ -0.5 V to VCC + 0.5 V
DC Output Voltage (TTL outputs .........................................................................................-0.5 V to VCC + 0.5V
Output Current (TTL outputs) ..................................................................................................................+/- 50mA
Output Current (Differential outputs).......................................................................................................+/- 50mA
Case Temperature Under Bias........................................................................................................-55o to + 100oC
Note: Caution: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing
permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.
Recommended Operating Conditions
Power Supply Voltages (VCC)............................................................................................................. +3.3V ±5 %
Operating Case Temperature Range (T)................................................................................................ 0o to 85oC
Notes: (1) Customer may require cooled/heatsink environment to meet thermal requirements of 100TQFP.
(2) Contact factory for package thermal performance information.
(3) θJC = 6oC/W
ESD Ratings
Proper ESD procedures should be used when handling this product. The VSC8124 is rated to the following ESD
voltages based on the human body model:
1. High speed pins are rated ≥ 200V
2. All other pins are rated at or above 1500V.
G52271-0, Rev. 1.14
2/23/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet VSC8124.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| VSC8122 | Multi-Rate SONET/SDH Clock and Data Recovery IC | Vitesse Semiconductor |
| VSC8124 | Target Specification | Vitesse Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |