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PDF AD9911 Data sheet ( Hoja de datos )
| Número de pieza | AD9911 | |
| Descripción | 500 MSPS Direct Digital Synthesizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
500 MSPS Direct Digital Synthesizer
with 10-Bit DAC
AD9911
FEATURES
Patented SpurKiller technology
Multitone generation
Test-tone modulation
Up to 800 Mbps data throughput
Matched latencies for frequency/phase/amplitude changes
Linear frequency/phase/amplitude sweeping capability
Up to 16 levels of FSK, PSK, ASK
Programmable DAC full-scale current
32-bit frequency tuning resolution
14-bit phase offset resolution
10-bit output amplitude-scaling resolution
Software-/hardware-controlled power-down
Multiple device synchronization
Selectable 4× to 20× REF_CLK multiplier (PLL)
Selectable REF_CLK crystal oscillator
56-lead LFCSP
APPLICATIONS
Agile local oscillator
Test and measurement equipment
Commercial and amateur radio exciter
Radar and sonar
Test-tone generation
Fast frequency hopping
Clock generation
GENERAL DESCRIPTION
The AD9911 is a complete direct digital synthesizer (DDS).
This device includes a high speed DAC with excellent wideband
and narrowband spurious-free dynamic range (SFDR) as well as
three auxiliary DDS cores without assigned digital-to-analog
converters (DACs). These auxiliary channels are used for spur
reduction, multitone generation, or test-tone modulation.
The AD9911 is the first DDS to incorporate SpurKiller
technology and multitone generation capability. Multitone
mode enables the generation up to four concurrent carriers;
frequency, phase and amplitude can be independently
programmed. Multitone generation can be used for system
tests, such as inter-modulation distortion and receiver blocker
sensitivity. SpurKilling enables customers to improve SFDR
performance by reducing the magnitude of harmonic
components and/or the aliases of those harmonic components.
Test-tone modulation efficiently enables sine wave modulation
of amplitude on the output signal using one of the auxiliary
DDS cores.
The AD9911 can perform modulation of frequency, phase, or
amplitude (FSK, PSK, ASK). Modulation is implemented by
storing profiles in the register bank and applying data to the
profile pins. In addition, the AD9911 supports linear sweep of
frequency, phase, or amplitude for applications such as radar
and instrumentation.
(continued on Page 3)
500MSPS
DDS CORE
10-BIT DAC
SYSTEM
CLOCK
SOURCE
SPUR REDUCTION/
MODULATION CONTROL
MULTITONE
REF CLOCK
INPUT CIRCUITRY
TIMING AND
CONTROL
RECONSTRUCTED
SINE WAVE
USER INTERFACE
Figure 1. Basic Block Diagram
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD9911
Parameter
Min Typ Max Unit Test Conditions/Comments
NARROWBAND SFDR
1.1 MHz Analog Output (±10 kHz)
−90 dBc
1.1 MHz Analog Output (±50 kHz)
−88 dBc
1.1 MHz Analog Output (±250 kHz)
−86 dBc
1.1 MHz Analog Output (±1 MHz)
−85 dBc
15.1 MHz Analog Output (±10 kHz)
−90 dBc
15.1 MHz Analog Output (±50 kHz)
−87 dBc
15.1 MHz Analog Output (±250 kHz)
−85 dBc
15.1 MHz Analog Output (±1 MHz)
−83 dBc
40.1 MHz Analog Output (±10 kHz)
−90 dBc
40.1 MHz Analog Output (±50 kHz)
−87 dBc
40.1 MHz Analog Output (±250 kHz)
−84 dBc
40.1 MHz Analog Output (±1 MHz)
−82 dBc
75.1 MHz Analog Output (±10 kHz)
−87 dBc
75.1 MHz Analog Output (±50 kHz)
−85 dBc
75.1 MHz Analog Output (±250 kHz)
−83 dBc
75.1 MHz Analog Output (±1 MHz)
−82 dBc
100.3 MHz Analog Output (±10 kHz)
−87 dBc
100.3 MHz Analog Output (±50 kHz)
−85 dBc
100.3 MHz Analog Output (±250 kHz)
−83 dBc
100.3 MHz Analog Output (±1 MHz)
−81 dBc
200.3 MHz Analog Output (±10 kHz)
−87 dBc
200.3 MHz Analog Output (±50 kHz)
−85 dBc
200.3 MHz Analog Output (±250 kHz)
−83 dBc
200.3 MHz Analog Output (±1 MHz)
−81 dBc
PHASE NOISE CHARACTERISTICS
Residual Phase Noise @ 15.1 MHz (fOUT)
1 kHz Offset
–150
dBc/Hz
10 kHz Offset
–159
dBc/Hz
100 kHz Offset
–165
dBc/Hz
1 MHz Offset
–165
dBc/Hz
Residual Phase Noise @ 40.1 MHz (fOUT)
1 kHz Offset
–142
dBc/Hz
10 kHz Offset
–151
dBc/Hz
100 kHz Offset
–160
dBc/Hz
1 MHz Offset
–162
dBc/Hz
Residual Phase Noise @ 75.1 MHz (fOUT)
1 kHz Offset
–135
dBc/Hz
10 kHz Offset
–146
dBc/Hz
100 kHz Offset
–154
dBc/Hz
1 MHz Offset
–157
dBc/Hz
Residual Phase Noise @ 100.3 MHz (fOUT)
1 kHz Offset
–134
dBc/Hz
10 kHz Offset
–144
dBc/Hz
100 kHz Offset
–152
dBc/Hz
1 MHz Offset
–154
dBc/Hz
Rev. A | Page 5 of 41
5 Page 
Data Sheet
Pin No.
6, 10, 12, 16, 28, 32
40, 41, 42, 43
Mnemonic
NC
P0, P1, P2, P3
46
47
48
49
50
51, 52, 53
54
I/O_UPDATE
CS
SCLK
DVDD_I/O
SDIO_0
SDIO_1, SDIO_2,
SDIO_3
SYNC_CLK
AD9911
I/O Description
N/A No Connection. Analog Devices recommends leaving these pins floating.
I These data pins are used for modulation (FSK, PSK, ASK), start/stop for the sweep
accumulator, and ramping up/down the output amplitude. Any toggle of these data
inputs is equivalent to an I/O_UPDATE. The data is synchronous to the SYNC_CLK (Pin
54). The data inputs must meet the set-up and hold time requirements to the
SYNC_CLK. This guarantees a fixed pipeline delay of data to the DAC output;
otherwise, a ±1 SYNC_CLK period of uncertainty occurs. The functionality of these
pins is controlled by profile pin configuration (PPC) bits in Register FR1 <12:14>.
I A rising edge triggers data transfer from the I/O port buffer to active registers.
I/O_UPDATE is synchronous to the SYNC_CLK (Pin 54). I/O_UPDATE must meet the
set-up and hold time requirements to the SYNC_CLK to guarantee a fixed pipeline
delay of data to DAC output. If not, a ±1 SYNC_CLK period of uncertainty occurs. The
minimum pulse width is one SYNC_CLK period.
I The active low chip select allows multiple devices to share a common I/O bus (SPI).
I Data Clock for I/O Operations. Data bits are written on the rising edge of SCLK and
read on the falling edge of SCLK.
I 3.3 V Digital Power Supply for SPI Port and Digital I/O.
I/O Data pin SDIO_0 is dedicated to the I/O port only.
I/O Data pins SDIO_1:3 can be used for the I/O port or to initiate a ramp up/ramp down
(RU/RD) of the DAC output amplitude.
O The SYNC_CLK, which runs at ¼ the system clock rate, can be disabled. I/O_UPDATE
and profile changes (Pin 40 to Pin 43) are synchronous to the SYNC_CLK. To guarantee
a fixed pipeline delay of data to DAC output, I/O_UPDATE and profile changes (Pin 40
to Pin 43) must meet the set-up and hold time requirements to the rising edge of
SYNC_CLK. If not, a ±1 SYNC_CLK period of uncertainty exists.
Rev. A | Page 11 of 41
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9911.PDF ] | |
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