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PDF HT82A832R Data sheet ( Hoja de datos )
| Número de pieza | HT82A832R | |
| Descripción | Basic USB Phone OTP MCU | |
| Fabricantes | Holtek Semiconductor | |
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HT82A832R
Basic USB Phone OTP MCU
Features
· Operating voltage: fSYS = 6M/12MHz: 4.0V~5.5V
· 24 bidirectional I/O lines (max.)
· Two 16-bit programmable timer/event counters and
overflow interrupts
· 4096´15 program memory ROM
· 192´8 data memory RAM (Bank 0)
· USB 2.0 full speed compatible
· USB spec V1.1 full speed operation and USB audio
device class spec V1.0
· Embedded high-performance 16 bit PCM ADC
· Built-in Digital PGA (Programmable Gain Amplifier)
· 48kHz/8kHz sampling rate for audio playback
controlled by software option
· 8kHz audio recording sampling rate
· Embedded class AB speaker driver power amplifier
· Embedded High Performance 16 bit audio DAC
· Supports audio playback digital volume control
· 5 endpoints supported (endpoint 0 included)
· Supports 1 Control, 2 Interrupt, 2 Isochronous
transfer
· Two hardware implemented Isochronous transfers
· Total FIFO size: 464 bytes
(8, 8, 384, 32, 32 for EP0~EP4)
· Programmable frequency divider (PFD)
· Integrated SPI hardware circuit
· Play/Record Interrupt
· HALT and wake-up features reduce power
consumption
· Watchdog Timer
· 16-level subroutine nesting
· Bit manipulation instruction
· 15-bit table read instruction
· 63 powerful instructions
· All instructions executed within one or two machine
cycles
· Low voltage reset function (3.0V±0.3V)
· 48-pin SSOP/LQFP package
General Description
The HT82A832R is an 8-bit high performance RISC-like
microcontroller designed for USB Phone product
applications. The HT82A832R combines a 16-bit PCM
ADC, USB transceiver, SIE (Serial Interface Engine),
audio class processing unit, FIFO and an 8-bit MCU into
a single chip. The DAC in the HT82A832R operates at a
sampling rate of 48kHz/8kHz and the 16-bit PCM ADC
operates at 8kHz for the Microphone input. For the
DAC, the HT82A832R has a digital programmable gain
amplifier. The gain range is from -32dB to +6dB. For the
ADC input, the digital gain range is from 0dB to 19.5dB.
Rev. 1.00
1 July 18, 2006
1 page  
www.DataSheet4U.com
HT82A832R
D.C. Characteristics
Ta=25°C
Symbol
Parameter
Test Conditions
VDD Conditions
Min. Typ. Max. Unit
VDD Operating Voltage
5V ¾
4.0 5.0 5.5
V
IDD Operating Current
5V
No load, fSYS=12MHz,
ADC On, DAC On
5V
No load, fSYS=12MHz,
ADC Off, DAC Off
¾ 12 ¾ mA
¾ 8 ¾ mA
ISUS Suspend Current
No load, system HALT,
5V USB transceiver and 3.3V ¾ 330 ¾ mA
regulator on
VIL1 Input Low Voltage for I/O Ports 5V
¾
0 ¾ 0.3VDD V
VIH1 Input High Voltage for I/O Ports 5V
¾ 0.7VDD ¾ VDD V
VIL2 Input Low Voltage (RESET)
5V
¾
0 ¾ 0.4VDD V
VIH2 Input High Voltage (RESET)
5V
¾ 0.9VDD ¾ VDD V
IOL I/O Port Sink Current
5V VOL=0.1VDD
¾ 5 ¾ mA
IOH I/O Port Source Current
5V VOH=0.7VDD
¾ -5 ¾ mA
RPH Pull-high Resistance
5V
¾
30 40 80 kW
VLVR Low Voltage Reset
5V ¾
2.7 3.0 3.3
V
VV33O 3.3V Regulator Output
5V IV33O=-5mA
3.0 3.3 3.6
V
DAC+Power Amp:
Test condition: Measurement bandwidth 20Hz to 20kHz, fS= 48kHz. Line output series capacitor with 220mF.
THD+N THD+NNote1
4W load
5V
8W load
¾ -30 ¾
¾ -35 ¾
dB
SNRDA Signal to Noise RatioNote1
4W load
5V
8W load
¾ 81 ¾
dB
¾ 82 ¾
DR Dynamic Range
4W load
5V
8W load
¾ 87 ¾
dB
¾ 88 ¾
POUT Output Power
4W load, THD=10%
5V
8W load, THD=10%
¾ 400 ¾
mW/ch
¾ 200 ¾
PCM ADC
SNRAD Signal to Noise Ratio
5V
¾
¾ 77 ¾ dB
VAG Reference Voltage
5V ¾
¾2¾V
VPEAK
Peak Single Frequency Tone
Amplitude without Clipping
5V
¾
¾ 1.575 ¾
VPK
Note.1: Sine wave input at 1kHz, -6dB
A.C. Characteristics
Symbol
Parameter
Test Conditions
VDD Conditions
fSYS System Clock (Crystal OSC)
5V
¾
tWDTOSC Watchdog Oscillator Period
5V
¾
tRES RESET Input Pulse Width
¾
¾
tSST System Start-up Timer Period ¾
¾
tINT Interrupt Pulse Width
¾
¾
Note: tSYS=1/fSYS
Ta=25°C
Min. Typ. Max. Unit
0.4 ¾ 12 MHz
¾ 100 ¾
ms
1 ¾ ¾ ms
¾ 1024 ¾
tSYS
1 ¾ ¾ ms
Rev. 1.00
5 July 18, 2006
5 Page 
www.DataSheet4U.com
HT82A832R
Bit No.
0
1
2
3
4
5
6
7
Label
EMI
EUI
ET0I
ET1I
USBF
T0F
T1F
¾
Function
Controls the master (global) interrupt (1=enable; 0=disable)
Controls the USB interrupt (1=enable; 0=disable)
Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)
Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable)
USB interrupt request flag (1=active; 0=inactive)
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
Unused bit, read as ²0²
INTC0 (0BH) Register
Bit No.
0
1
2
3, 7
4
5
6
Label
Function
EPLAYI Play interrupt (1=enable; 0=disable)
ESII Control Serial interface interrupt (1=enable; 0=disable)
RECI Record interrupt (1=enable; 0=disable)
¾ Unused bit, read as ²0²
PLAYF Play interrupt request flag (1=active; 0=inactive)
SIF Serial interface interrupt request flag (1=active; 0=inactive)
RECF Record interrupt request flag (1=active; 0=inactive)
INTC1 (1EH) Register
related interrupt request flag (T1F) will be reset and the
EMI bit cleared to disable further interrupts.
The play interrupt is initialized by setting the play
interrupt request flag (bit 4 of INTC1), caused by a play
data valid. When the interrupt is enabled, the stack is not
full and the PLAYF is set, a subroutine call to location
10H will occur. The related interrupt request flag
(PLAYF) will be reset and the EMI bit cleared to disable
further interrupts. If PLAY_MODE (bit 3 of MODE_CTRL
register) is set to ²1², the play interrupt frequency will
change to 8KHz, otherwise the interrupt frequency is
48kHz.
The serial interface interrupt is indicated by the interrupt
flag (SIF; bit 5 of INTC1), that is generated by the
reception or transfer of a complete 8-bits of data
between the HT82A832R and the external device. The
serial interface interrupt is controlled by setting the
Serial interface interrupt control bit (ESII; bit 1 of
INTC1). After the interrupt is enabled (by setting SBEN;
bit 4 of SBCR), and the stack is not full and the SIF is set,
a subroutine call to location 14H occurs.
The record interrupt is initialized by setting the record
interrupt request flag (bit 6 of INTC1), caused by a
record data valid. When the interrupt is enabled, the
stack is not full and RECF is set, a subroutine call to
location 18H will occur. The related interrupt request flag
(RECF) will be reset and the EMI bit cleared to disable
further interrupts. If ADC powered down (AD_ENB =1)
or USB clock disabled (USBCKEN=0), the record
interrupt will be disabled.
During the execution of an interrupt subroutine, other
interrupt acknowledge signals are held until the ²RETI²
instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding
interrupts are enabled. In the case of simultaneous
requests the following table shows the priority that is
applied. These can be masked by resetting the EMI bit.
Interrupt Source
Priority
USB interrupt
1
Timer/Event Counter 0 overflow 2
Timer/Event Counter 1 overflow 3
Play Interrupt
4
Serial Interface Interrupt
5
Record Interrupt
6
Vector
04H
08H
0CH
10H
14H
18H
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be
damaged once the ²CALL² operates in the interrupt
subroutine.
Rev. 1.00
11 July 18, 2006
11 Page | ||
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| PDF Descargar | [ Datasheet HT82A832R.PDF ] | |
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