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PDF MPC8347EA Data sheet ( Hoja de datos )
| Número de pieza | MPC8347EA | |
| Descripción | Integrated Host Processor Hardware Spec | |
| Fabricantes | Motorola Semiconductor | |
| Logotipo |  |
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Freescale Semiconductor
Technical Data
MPC8347EAEC
Rev. 2, 8/2006
MPC8347EA PowerQUICC™ II Pro
Integrated Host Processor Hardware
Specifications
The MPC8347EA contains a PowerPC™ processor core
(built on Power Architecture™ technology) with system
logic for networking, storage, and general-purpose
embedded applications. For functional characteristics of the
processor, refer to the MPC8349EA PowerQUICC™ II Pro
Integrated Host Processor Reference Manual, Rev. 0.
To locate published errata or updates for this document,
contact your Freescale sales office.
NOTE
The information in this document is accurate
for revision 3.0 silicon and later. For
information on revision 1.1 silicon and earlier
versions, see the MPC8347E
PowerQUICC™ II Pro Integrated Host
Processor Hardware Specifications. See
Section 23.1, “Part Numbers Fully
Addressed by this Document,” for silicon
revision level determination.
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 16
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 19
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8. Ethernet: Three-Speed Ethernet, MII Management . 29
9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
13. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
14. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
15. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
17. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
18. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 70
19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
21. System Design Information . . . . . . . . . . . . . . . . . . 111
22. Document Revision History . . . . . . . . . . . . . . . . . . 117
23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 117
© Freescale Semiconductor, Inc., 2006. All rights reserved.
1 page  
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Overview
– Enhanced host controller interface (EHCI) compatible
– Complies with USB specification Rev. 2.0
— High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
— Direct connection to a high-speed device without an external hub
— External PHY with serial and low-pin count (ULPI) interfaces
• Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 133 MHz
— Eight chip selects for eight external slaves
— Up to eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller
— Three protocol engines on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user-programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
• Programmable interrupt controller (PIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for 8 external and 35 internal discrete interrupt sources
— Support for 1 external (optional) and 7 internal machine checkstop interrupt sources
— Programmable highest priority request
— Four groups of interrupts with programmable priority
— External and internal interrupts directed to host processor
— Redirects interrupts to external INTA pin in core disable mode.
— Unique vector number for each interrupt source
• Dual industry-standard I2C interfaces
— Two-wire interface
— Multiple master support
— Master or slave I2C mode support
— On-chip digital filtering rejects spikes on the bus
— System initialization data optionally loaded from I2C-1 EPROM by boot sequencer embedded
hardware
• DMA controller
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— Handshaking (external control) signals for all channels: DMA_DREQ[0:3],
DMA_DACK[0:3], DMA_DDONE[0:3]
— All channels accessible to local core and remote PCI masters
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
5
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Electrical Characteristics
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MPC8347EA.PDF ] | |
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