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PDF MAX9451 Data sheet ( Hoja de datos )
| Número de pieza | MAX9451 | |
| Descripción | (MAX9450 - MAX9452) High-Precision Clock Generators | |
| Fabricantes | Maxim Integrated Products | |
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19-0547; Rev 2; 9/06
High-Precision Clock Generators
with Integrated VCXO
General Description
The MAX9450/MAX9451/MAX9452 clock generators
provide high-precision clocks for timing in SONET/SDH
systems or Gigabit Ethernet systems. The MAX9450/
MAX9451/MAX9452 can also provide clocks for the high-
speed and high-resolution ADCs and DACs in 3G base
stations. Additionally, the devices can also be used as a
jitter attenuator for generating high-precision CLK signals.
The MAX9450/MAX9451/MAX9452 feature an integrated
VCXO. This configuration eliminates the use of an exter-
nal VCXO and provides a cost-effective solution for gen-
erating high-precision clocks. The MAX9450/MAX9451/
MAX9452 feature two differential inputs and clock out-
puts. The inputs accept LVPECL, LVDS, differential sig-
nals, and LVCMOS. The input reference clocks range
from 8kHz to 500MHz.
The MAX9450/MAX9451/MAX9452 offer LVPECL, HSTL,
and LVDS outputs, respectively. The output range is up
to 160MHz, depending on the selection of crystal. The
input and output frequency selection is implemented
through the I2C or SPI™ interface. The MAX9450/
MAX9451/MAX9452 feature clock output jitter less than
0.8ps RMS (in a 12kHz to 20MHz band) and phase-
noise attenuation greater than -130dBc/Hz at 100kHz.
The phase-locked loop (PLL) filter can be set externally,
and the filter bandwidth can vary from 1Hz to 20kHz.
The MAX9450/MAX9451/MAX9452 feature an input
clock monitor with a hitless switch. When a failure is
detected at the selected reference clock, the device
can switch to the other reference clock. The reaction to
the recovery of the failed reference clock can be
revertive or nonrevertive. If both reference clocks fail,
the PLL retains its nominal frequency within a range of
±20ppm at +25°C.
The MAX9450/MAX9451/MAX9452 operate from 2.4V to
3.6V supply and are available in 32-pin TQFP packages
with exposed pads.
Applications
SONET/SDH Systems
10 Gigabit Network Routers and Switches
3G Cellular Phone Base Stations
General Jitter Attenuation
Features
♦ Integrated VCXO Provides a Cost-Effective
Solution for High-Precision Clocks
♦ 8kHz to 500MHz Input Frequency Range
♦ 15MHz to 160MHz Output Frequency Range
♦ I2C or SPI Programming for the Input and Output
Frequency Selection
♦ PLL Lock Range > ±60ppm
♦ Two Differential Outputs with Three Types of
Signaling: LVPECL, LVDS, or HSTL
♦ Input Clock Monitor with Hitless Switch
♦ Internal Holdover Function within ±20ppm of the
Nominal Frequency
♦ Low Output CLK Jitter: < 0.8ps RMS in the 12kHz
to 20MHz Band
♦ Low Phase Noise > -130dBc at 100kHz, > -140dBc
at 1MHz
Ordering Information
PART
PIN-PACKAGE OUTPUT PKG CODE
MAX9450EHJ 32 TQFP-EP*
LVPECL
H32E-6
MAX9451EHJ 32 TQFP-EP*
HSTL
H32E-6
MAX9452EHJ 32 TQFP-EP*
LVDS
H32E-6
Note: All devices are specified over the -40°C to +85°C
temperature range.
For lead-free packages, contact factory.
*EP = Exposed paddle.
Pin Configuration
TOP VIEW
24 23 22 21 20 19 18 17
VDD 25
X1 26
X2 27
VDDA 28
LP1 29
LP2 30
GNDA 31
RJ 32
MAX9450
MAX9451
MAX9452
EXPOSED PAD
(GND)
16 CMON
15 AD1
14 AD0
13 SDA
12 SCL
11 GND/CS
10 MR
9 INT
123 45 67 8
SPI is a trademark of Motorola, Inc.
TQFP
(5mm x 5mm)
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
High-Precision Clock Generators
with Integrated VCXO
Typical Operating Characteristics
(VDD = VDDA = VDDQ = 3.3V. TA = +25°C, unless otherwise noted.)
VDD AND VDDA SUPPLY CURRENT
vs. VOLTAGE (MAX9450)
80
VDDQ SUPPLY CURRENT
vs. VOLTAGE (MAX9450)
80
OUTPUT RMS JITTER
vs. TEMPERATURE
10
72
TA = +25°C
64 TA = -40°C
72
TA = -40°C
TA = +25°C
64
8
6
56 56
TA = +85°C
48
TA = +85°C
48
4
2
40
2.4 2.6 2.8 3.0 3.2 3.4 3.6
VOLTAGE (V)
40
2.4 2.6 2.8 3.0 3.2 3.4 3.6
VOLTAGE (V)
0
-40 -15 10 35 60
TEMPERATURE (°C)
85
OUTPUT FREQUENCY CHANGE
vs. TEMPERATURE
40
20
0
-20
-40
-40
-15 10 35 60
TEMPERATURE (°C)
85
PHASE NOISE
vs. FREQUENCY
0
INPUT REFERENCE = 38.88 MHz
-20 OUTPUT CLOCK = 155.52 MHz
-40
-60
-80
-100
-120
-140
-160
1k
10k 100k 1M
FREQUENCY (Hz)
MAX9450 toc05
153.13mV/div
100mV/div
OUTPUT CLOCK SYNCHRONIZED
TO INPUT REFERENCE
MAX9450 toc06
INPUT REFERENCE = 19.44MHz
OUTPUT CLOCK = 155.52 MHz
10M 10ns/div
_______________________________________________________________________________________ 5
5 Page 
High-Precision Clock Generators
with Integrated VCXO
Data Transfer and Acknowledge
Following the START condition, each SCL clock pulse
transfers 1 bit. Between a START and a STOP, multiple
bytes can be transferred on the 2-wire bus. The first 7 bits
(B0–B6) are for the device address. The eighth bit (B7)
indicates the writing (low) or reading (high) operation
(W/R). The ninth bit (B8) is the ACK for the address and
operation type. A low ACK bit indicates a successful
transfer; otherwise, a high ACK bit indicates an unsuc-
cessful transfer. The next 8 bits (register address),
B9–B16, form the address byte for the control register
to be written (Figure 4). The next bit, bit 17, is the ACK
for the register address byte. The following byte (Data1)
is the content to be written into the addressed register
of the slave. After this, the address counter of I2C is
increased by 1 (Rgst Addr + 1) and the next byte
(Data2) writes into a new register. To read the contents
in the MAX9450/MAX9451/MAX9452s’ control registers,
the master sends the register address to be read to the
slave by a writing operation. Then it sends the byte of
device address + R to the slave. The slave (MAX9450/
MAX9451/MAX9452) responds with the content bytes
from the registers, starting from the pointed register to
the last register, CR8, consecutively back to the master
(Figures 5 and 6).
Write Byte Format
S ADDRESS WR ACK
COMMAND
ACK
DATA
ACK
P
— 7 bits
—
Slave address: equiva-
lent to chip-select line of
a 3-wire interface
Read Byte Format
— 8 bits — 8 bits — 1
Command byte: selects to
which register you are writing
Data byte: data goes into the register
set by the command byte (to set
thresholds, configuration masks, and
sampling rate)
S ADDRESS WR ACK COMMAND ACK
S ADDRESS RD ACK DATA
///
P
— 7 bits
——
Slave address: equivalent
to chip-select line
Send Byte Format
8 bits
—
Command byte: selects
from which register you
are reading
— 7 bits — —
Slave address: repeated
due to change in data-
flow direction
Receive Byte Format
8 bits — —
Data byte: reads from
the register set by the
command byte
S ADDRESS WR ACK COMMAND ACK P
— 7 bits
——
8 bits
——
Command byte: sends com-
mand with no data, usually
used for one-shot command
S = Start condition
P = Stop condition
Shaded = Slave transmission
/// = Not acknowledged
Figure 4. I2C Interface Data Structure
S ADDRESS RD ACK DATA ///
P
— 7 bits — — 8 bits — —
Data byte: reads data from the register
commanded by the last read byte or
write byte transmission; also used for
SMBus alert response return address
SMBCLK
AB
tLOW tHIGH
C
D EF
G
H IJK
LM
SMBDATA
tSU:STA tHD:STA
tSU:DAT
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
Figure 5. SMBus Write Timing Diagram
E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE
H = LSB OF DATA CLOCKED INTO SLAVE
tSU:STO tBUF
I = MASTER PULLS DATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO SLAVE
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION
M = NEW START CONDITION
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet MAX9451.PDF ] | |
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