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PDF MC56F8345 Data sheet ( Hoja de datos )
| Número de pieza | MC56F8345 | |
| Descripción | 16-bit Hybrid Controller | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Freescale Semiconductor, Inc.
MC56F8345/D
Rev. 8.0, 6/2004
Preliminary Technical Data
56F8345 16-bit Hybrid Controller
56F8345
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 128KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• Two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
• Two Quadrature Decoders
• FlexCAN module
• Optional On-Chip Regulator
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interface (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 49 GPIO lines
• 128-pin LQFP Package
6 PWM Outputs
3 Current Sense Inputs
or GPIOC
4 Fault Inputs
PWMA
6 PWM Outputs
3 Current Sense Inputs
or GPIOD
4 Fault Inputs
PWMB
4 AD0
4
ADCA
AD1
Memory
5 VREF
Program Memory
4 AD0
64K x 16 Flash
ADCB
2K x 16 RAM
4 AD1
4K x 16 Boot
Flash
TEMP_SENSE
Quadrature Data Memory
4
Decoder 0 or
Quad
4K x 16 Flash
4K x 16 RAM
Timer A or
GPIOC
Quadrature
4 Decoder 1 or
Quad
Timer B or
SP1I or
GPIOC Decoding
2 Quad Timer Peripherals
C or GPIOE
4 Quad Timer
D or GPIOE
2 FlexCAN
SPI0 or
GPIOE
RSTO
RESET
5
VPP
2
OCR_DIS
VCAP VDD VSS VDDA
47
52
VSSA
JTAG/
EOnCE
Port
Digital Reg Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Program Controller
Address
and Hardware Generation Unit
Looping Unit
Data ALU
16 x 16 + 36 -->36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
System Bus
Control
* External
Address Bus
Switch
6
5
* External
Data
Bus Switch
4
A8-13 or GPIOA0-5
GPIOB0-4 or A16-20
D7-10 or GPIOF0-3
IPBus Bridge (IPBB)
* Bus
Control
6
GPIOD0-5 or CS2-7
Peripheral
Device Selects
RW IPAB IPWDB
Control
IPRDB
Clock
resets
PLL
* EMI not functional in
this package; use as
GPIO pins
SCI1 or SCI0 or COP/ Interrupt
GPIOD GPIOE Watchdog Controller
System
P
O
Integration R
Module
Clock O
Generator
S
C
XTAL
EXTAL
4 22
IRQA IRQB
CLKO
CLKMODE
56F8345 Block Diagram - 128 LQFP
© Motorola, Inc., 2004. All rights reserved.
For More Information On This Product,
Go to: www.freescale.com
1 page  
Freescale Semiconductor, Inc.
56F8345 Description
• FlexCAN (CAN Version 2.0 B-compliant) module with 2-pin port for transmit and receive
• Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines)
• Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional
GPIO lines); SPI 1 can also be used as Quadrature Decoder 1 or Quad Timer B
• Computer Operating Properly (COP)/Watchdog timer
• Two dedicated external interrupt pins
• 49 General Purpose I/O (GPIO) pins; 21 pins dedicated to GPIO
• External reset input pin for hardware reset
• External reset output pin for system reset
• Integrated low-voltage interrupt module
• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent,
real-time debugging
• Software-programmable, Phase Lock Loop-based frequency synthesizer for the core clock
1.1.4 Energy Information
• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
• On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be
disabled
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
• ADC smart power management
• Each peripheral can be individually disabled to save power
1.2 56F8345 Description
The 56F8345 is a member of the 56800E core-based family of hybrid controllers. It combines, on
a single chip, the processing power of a DSP and the functionality of a microcontroller with a
flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56F8345 is well-suited for many
applications. The 56F8345 includes many peripherals that are especially useful for motion control,
smart appliances, steppers, encoders, tachometers, limit switches, power supply and control,
automotive control, engine management, noise suppression, remote utility metering, industrial
control for power, lighting, and automation applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units
operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style
programming model and optimized instruction set allow straightforward generation of efficient,
compact DSP and control code. The instruction set is also highly efficient for C/C++ Compilers to
enable rapid development of optimized control applications.
The 56F8345 supports program execution from internal memories. Two data operands can be
accessed from the on-chip data RAM per instruction cycle. The 56F8345 also provides two
external dedicated interrupt lines and up to 49 General Purpose Input/Output (GPIO) lines,
depending on peripheral configuration.
The 56F8345 hybrid controller includes 128KB of Program Flash and 8KB of Data Flash (each
programmable through the JTAG port) with 4KB of Program RAM and 8KB of Data RAM.
A total of 8KB of Boot Flash is incorporated for easy customer-inclusion of field-programmable
56F8345 Technical Data
Preliminary
For More Information On This Product,
Go to: www.freescale.com
5
5 Page 
Freescale Semiconductor, Inc.
Data Sheet Conventions
1.6 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Examples:
Signal/Symbol
Logic State
Signal State
Voltage1
PIN
True
Asserted
VIL/VOL
PIN
False
Deasserted
VIH/VOH
PIN
True
Asserted
VIH/VOH
PIN
False
Deasserted
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
VIL/VOL
56F8345 Technical Data
Preliminary
For More Information On This Product,
Go to: www.freescale.com
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MC56F8345.PDF ] | |
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