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PDF STD9N10-1 Data sheet ( Hoja de datos )

Número de pieza STD9N10-1
Descripción N-CHANNEL POWER MOS TRANSISTOR
Fabricantes ST Microelectronics　
Logotipo ST Microelectronics Logotipo



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STD9N10
STD9N10-1
N-CHANNEL 100V - 0.23 Ω - 9A DPAK/IPAK
POWER MOS TRANSISTOR
Table 1. General Features
Type
VDSS
RDS(on)
STD9N10
100 V
< 0.27 Ω
STD9N10-1
100 V
< 0.27 Ω
ID
9A
9A
FEATURES SUMMARY
■ TYPICAL RDS(on) = 0.23 Ω
■ AVALANCHE RUGGED TECHNOLOGY
■ 100% AVALANCHE TESTED
■ REPETITIVE AVALANCHE DATA AT 100°C
■ LOW GATE CHARGE
■ HIGH CURRENT CAPABILITY
■ 175°C OPERATING TEMPERATURE
■ APPLICATION ORIENTED
CHARACTERIZATION
■ THROUGH-HOLE IPAK (TO-251) POWER
PACKAGE IN TUBE (SUFFIX "-1")
■ SURFACE-MOUNTING DPAK (TO-252)
POWER PACKAGE IN TAPE & REEL
(SUFFIX "T4")
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SOLENOID AND RELAY DRIVERS
■ REGULATORS
■ DC-DC & DC-AC CONVERTERS
■ MOTOR CONTROL, AUDIO AMPLIFIERS
■ AUTOMOTIVE ENVIRONMENT (INJECTION,
ABS, AIR-BAG, LAMPDRIVERS, Etc.)
Figure 1. Package
3
2
1
IPAK
TO-251
3
1
DPAK
TO-252
Figure 2. Internal Schematic Diagram
Table 2. Order Codes
Part Number
STD9N10T4
STD9N10-1
Marking
D9N10
D9N10
Package
DPAK
IPAK
Packaging
TAPE & REEL
TUBE
May 2004
REV. 2
1/12

1 page




STD9N10-1 pdf
Figure 7. Transfer Characteristics
STD9N10/STD9N10-1
Figure 8. Transconductance
Figure 9. Static Drain-source On Resistance
Figure 10. Gate Charge vs Gate-source Voltage
Figure 11. Capacitance Variations
Figure 12. Normalized Gate Threshold Voltage
vs Temperature
5/12

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STD9N10-1 arduino
STD9N10/STD9N10-1
REVISION HISTORY
Table 14. Revision History
Date
Revision
March-1996
1
3-May-2004
2
Description of Changes
First Issue
Stylesheet update. No content change.
11/12

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