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PDF LTC4267 Data sheet ( Hoja de datos )

Número de pieza LTC4267
Descripción Power over Ethernet IEEE 802.3af PD Interface
Fabricantes Linear Technology 
Logotipo Linear Technology Logotipo



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LTC4267
Power over Ethernet
IEEE 802.3af PD Interface with
Integrated Switching Regulator
FEATURES
Complete Power Interface Port for IEEE 802®.3af
Powered Device (PD)
Onboard 100V, 400mA UVLO Switch
Precision Dual Level Inrush Current Limit
Integrated Current Mode Switching Regulator
Onboard 25kΩ Signature Resistor with Disable
Programmable Classification Current (Class 0-4)
Thermal Overload Protection
Power Good Signal
Integrated Error Amplifier and Voltage Reference
Low Profile 16-Pin SSOP and 3mm × 5mm DFN
Packages
U
APPLICATIO S
IP Phone Power Management
Wireless Access Points
Security Cameras
Power over Ethernet
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
802 is a registered trademark of Institute of Electrical and Electronics Engineers, Inc.
DESCRIPTIO
The LTC®4267 combines an IEEE 802.3af compliant Pow-
ered Device (PD) interface with a current mode switching
regulator, providing a complete power solution for PD
applications. The LTC4267 integrates the 25kΩ signature
resistor, classification current source, thermal overload pro-
tection, signature disable and power good signal along with
an undervoltage lockout optimized for use with the IEEE-
required diode bridge. The precision dual level input current
limit allows the LTC4267 to charge large load capacitors
and interface with legacy PoE systems.
The current mode switching regulator is designed for
driving a 6V rated N-channel MOSFET and features pro-
grammable slope compensation, soft-start, and constant
frequency operation, minimizing noise even with light
loads. The LTC4267 includes an onboard error amplifier
and voltage reference allowing use in both isolated and
nonisolated configurations.
The LTC4267 is available in space saving, low profile
16-pin SSOP or DFN packages.
TYPICAL APPLICATIO
–48V
FROM
DATA PAIR
+
HD01
–48V
FROM
SPARE PAIR
+
HD01
Class 2 PD with 3.3V Isolated Power Supply
PA1133 SBM1040
VPORTP
PVCC
SMAJ58A
PWRGD
LTC4267
NGATE
0.1µF
SENSE
RCLASS
68.1
1%
RCLASS ITH/RUN
VFB
SIGDISA PGND
VPORTN
POUT
10k
+ PVCC + 5µF
4.7µF
MIN
320µF
10k Si3440
PVCC
0.1
6.8k
BA5516
PS2911
470
22nF
3.3V
1.5A
CHASSIS
100k
TLV431
60.4k
4267 TA01
4267f
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LTC4267 pdf
TYPICAL PERFOR A CE CHARACTERISTICS
LTC4267
Input Current vs Input Voltage
25k Detection Range
0.5
TA = 25°C
0.4
0.3
0.2
0.1
0
0
–2 –4 –6 –8
VPORTN VOLTAGE (V)
–10
4267 G01
Input Current vs Input Voltage
3
EXCLUDES ANY LOAD CURRENT
TA = 25°C
2
1
0
–40
–45 –50 –55
VPORTN VOLTAGE (V)
–60
4267 G04
Power Good Output Low Voltage
vs Current
4
TA = 25°C
3
2
1
0
0 2 4 6 8 10
CURRENT (mA)
4267 G07
Input Current vs Input Voltage
50
TA = 25°C
CLASS 4
40
30 CLASS 3
20
10
0
0
CLASS 2
CLASS 1
CLASS 0
–10 –20 –30 –40 –50 –60
VPORTN VOLTAGE (V)
4267 G02
Signature Resistance vs
Input Voltage
28
27
RESISTANCE
=
V
I
=
V2
I2
V1
I1
DIODES: S1B
TA = 25C
IEEE UPPER LIMIT
26
25 LTC4267 + 2 DIODES
24
LTC4267 ONLY IEEE LOWER LIMIT
23
22
V1: –1
V2: –2
–3 –5 –7
–4 –6 –8
VPORTN VOLTAGE (V)
–9
–10
4267 G05
POUT Leakage Current
120
VIN = 0V
TA = 25°C
90
60
30
0
0 20 40 60
POUT PIN VOLTAGE (V)
4267 G08
Input Current vs Input Voltage
12.0
CLASS 1 OPERATION
11.5
11.0
85°C
10.5
–40°C
10.0
9.5
9.0
–12
–14 –16 –18 –20
VPORTN VOLTAGE (V)
–22
4267 G03
Normalized UVLO Threshold vs
Temperature
2
APPLICABLE TO TURN-ON
AND TURN-0FF THRESHOLDS
1
0
–1
–2
–40 –20
0 20 40 60
TEMPERATURE (C)
80
4267 G06
Current Limit vs Input Voltage
400
85°C
– 40°C
HIGH CURRENT MODE
300
200
100
–40
LOW CURRENT MODE
85°C
– 40°C
–45 –50 –55
VPORTN VOLTAGE (V)
–60
4267 G09
4267f
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LTC4267 arduino
LTC4267
APPLICATIO S I FOR ATIO
Series Diodes
The IEEE 802.3af-defined operating modes for a PD refer-
ence the input voltage at the RJ45 connector on the PD.
The PD must be able to accept power of either polarity
at each of its inputs, so it is common to install diode
bridges (Figure 2). The LTC4267 takes this into account
by compensating for these diode drops in the threshold
points for each range of operation. A similar adjustment
is made for the UVLO voltages.
Detection
During detection, the PSE will apply a voltage in the
range of –2.8V to –10V on the cable and look for a 25kΩ
signature resistor. This identifies the device at the end of
the cable as a PD. With the terminal voltage in this range,
the LTC4267 connects an internal 25kΩ resistor between
the VPORTP and VPORTN pins. This precision, temperature
compensated resistor presents the proper signature to
alert the PSE that a PD is present and desires power to be
applied. The internal low-leakage UVLO switch prevents
the switching regulator circuitry from affecting the detec-
tion signature.
The LTC4267 is designed to compensate for the voltage
and resistance effects of the IEEE required diode bridge.
The signature range extends below the IEEE range to ac-
commodate the voltage drop of the two diodes. The IEEE
specification requires the PSE to use a ΔV/ΔI measurement
technique to keep the DC offset of these diodes from af-
fecting the signature resistance measurement. However,
the diode resistance appears in series with the signature
resistor and must be included in the overall signature
resistance of the PD. The LTC4267 compensates for the
two series diodes in the signature path by offsetting the
resistance so that a PD built using the LTC4267 will meet
the IEEE specification.
In some applications it is necessary to control whether or
not the PD is detected. In this case, the 25kΩ signature
resistor can be enabled and disabled with the use of the
SIGDISA pin (Figure 3). Disabling the signature via the
SIGDISA pin will change the signature resistor to 9kΩ
(typical) which is an invalid signature per the IEEE 802.3af
specification. This invalid signature is present for PD input
voltages from –2.8V to –10V. If the input rises above –10V,
the signature resistor reverts to 25kΩ to minimize power
dissipation in the LTC4267. To disable the signature, tie
SIGDISA to VPORTP. Alternately, the SIGDISA pin can be
driven high with respect to VPORTN. When SIGDISA is high,
all functions of the PD interface are disabled.
RJ45
TX+
1
TX
2 RX+
3
POWERED DEVICE (PD)
INTERFACE
AS DEFINED
BY IEEE 802.3af
RX
6
SPARE+
4
5
7 SPARE
8
T1
TO PHY
BR2
BR1
8
VPORTP
LTC4267
D3
4 VPORTN
4267 F02
Figure 2. LTC4267 PD Front End Using
Diode Bridges on Main and Spare Inputs
4267f
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