PDF AS6VA25616 Data sheet ( Hoja de datos )

Número de pieza	AS6VA25616
Descripción	low-power CMOS SRAM
Fabricantes	Alliance Semiconductor
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No Preview Available ! www.DataSheet4U.com October 2000 AS6VA25616 ® 2.7V to 3.3V 256K × 16 Intelliwatt™ low-power CMOS SRAM with one chip enable Features • AS6VA25616 • Intelliwatt™ active power circuitry • Industrial and commercial temperature ranges available • Organization: 262,144 words × 16 bits • 2.7V to 3.3V at 55 ns • Low power consumption: ACTIVE - 132 mW at 3.3V and 55 ns • Low power consumption: STANDBY - 66 µW max at 3.3V Logic block diagram A0 A1 A2 A3 A4 A6 A7 A8 A12 A13 I/O1–I/O8 I/O9–I/O16 I/O buffer 256K × 16 Array (4,194,304) VCC VSS Control circuit WE Column decoder UB OE LB CS • 1.2V data retention • Equal access and cycle times • Easy memory expansion with CS, OE inputs • Smallest footprint packages - 48-ball FBGA - 400-mil 44-pin TSOP II • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA Pin arrangement (top view) 44-pin 400-mil TSOP II A4 1 44 A3 2 43 A2 3 42 A1 4 41 A0 5 40 CS 6 39 I/O1 7 38 I/O2 8 37 I/O3 9 36 I/O4 10 35 I/VOVC5SCS 11 12 13 34 33 32 I/O6 14 31 I/O7 15 30 I/O8 16 29 WE 17 28 A17 18 27 A16 19 26 A15 20 25 A14 21 24 A13 22 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 VVI/OSCSC12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 A12 48-CSP Ball-Grid-Array Package 123456 A LB OE A0 A1 A2 NC B I/O9 UB A3 A4 CS I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D VSS I/O12 A17 A7 I/O4 VCC E VCC I/O13 NC A16 I/O5 VSS F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 NC A12 A13 WE I/O8 H NC A8 A9 A10 A11 NC Selection guide Product AS6VA25616 Min (V) 2.7 VCC Range Typ2 (V) 3.0 Max (V) 3.3 Speed (ns) 55 Power Dissipation Operating (ICC) Max (mA) Standby (ISB1) Max (µA) 2 20 10/6/00 ALLIANCE SEMICONDUCTOR 1 Copyright ©2000 Alliance Semiconductor. All rights reserved. 1 page AS6VA25616 ® Write cycle (over the operating range)11 Parameter Write cycle time Chip select to write end Address setup to write end Address setup time Write pulse width Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end UB/LB low to end of write Shaded areas indicate preliminary information. Symbol tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW tBW Min 55 40 40 0 35 0 25 0 0 5 35 Max Unit – ns – ns – ns – ns – ns – ns – ns – ns 20 ns – ns – ns Write waveform 1 (WE controlled)10,11 Address CS LB, UB WE tAS tWC tCW tBW tAW DIN DOUT Data undefined tWZ tAH tWP tDW tDH Data valid tOW High Z Write waveform 2 (CS controlled)10,11 Address CS LB, UB WE DIN DOUT tAS tCLZ High Z tWC tCW tAW tBW tWP tWZ Data undefined tDW tAH tDH Data valid tOW High Z Notes 12 12 4, 5 4, 5 4, 5 10/6/00 ALLIANCE SEMICONDUCTOR 5 5 Page

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