PDF AS6UA51216 Data sheet ( Hoja de datos )

Número de pieza	AS6UA51216
Descripción	low power CMOS SRAM
Fabricantes	Alliance Semiconductor
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No Preview Available ! www.DataSheet4U.com Advance Information June 2000 AS6UA51216 1.65V to 3.6V 512K×16 Intelliwatt™ low power CMOS SRAM with one chip enable Features • AS6UA51216 • Intelliwatt™ active power circuitry • Industrial and commercial temperature ranges available • Organization: 524,288 words × 16 bits • 2.7V to 3.6V at 55 ns • 2.3V to 2.7V at 70 ns • 1.65V to 2.3V at 100 ns • Low power consumption: ACTIVE - 144 mW at 3.6V and 55 ns - 68 mW at 2.7V and 70 ns - 28 mW at 2.3 V and 100 ns Logic block diagram A0 A1 A2 A3 A4 A6 A7 A8 A12 A13 I/O1–I/O8 I/O9–I/O16 I/O buffer 512K × 16 Array (8,388,608) VDD VSS Control circuit WE Column decoder UB OE LB CS Selection guide Product AS6UA51216 AS6UA51216 AS6UA51216 Min (V) 2.7 2.3 1.65 VCC Range Typ2 (V) 3.0 2.5 2.0 Max (V) 3.6 2.7 2.3 • Low power consumption: STANDBY - 72 µW max at 3.6V - 41 µW max at 2.7V - 28 µW max at 2.3V • 1.2V data retention • Equal access and cycle times • Easy memory expansion with CS, OE inputs • Smallest footprint packages - 48-ball FBGA - 400-mil 44-pin TSOP II • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA Pin arrangement (top view) 44-pin 400-mil TSOP II A4 A3 A2 A1 A0 CS I/O1 I/O2 I/O3 I/O4 I/VVOCS5CS I/O6 I/O7 I/O8 WE A18 A17 A16 A15 A14 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 VVI/CSOSC12 I/O11 I/O10 I/O9 A8 A9 A10 A11 A12 A13 Note: A “MODE” pad is to be placed between pins 33 and 34 and 11 and 12, shorted. The bonding of this pad to VCC or VSS configures the device. There should only be 44+2+2 pads on the chip. Two extra VCC to separate out Array from Peripheral and Two-Mode Pads. 48-CSP Ball-Grid-Array Package 123456 A LB OE A0 A1 A2 NC B I/O9 UB A3 A4 CS I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D VSS I/O12 A17 A7 I/O4 VCC E VCC I/O13 VSS A16 I/O5 VSS F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 NC A12 A13 WE I/O8 H A18 A8 A9 A10 A11 NC Speed (ns) 55 70 100 Power Dissipation Operating (ICC1) Max (mA) Standby (ISB2) Max (µA) 2 20 1 15 1 12 6/27/00 ALLIANCE SEMICONDUCTOR 1 Copyright ©2000 Alliance Semiconductor. All rights reserved. 1 page AS6UA51216 Write cycle (over the operating range) –55 Parameter Symbol Min Max Write cycle time tWC Chip enable to write end tCW Address setup to write end tAW Address setup time tAS Write pulse width tWP Address hold from end of write tAH Data valid to write end tDW Data hold time tDH Write enable to output in high Z tWZ Output active from write end tOW UB/LB low to end of write tBW Shaded areas indicate preliminary information. 55 40 40 0 35 0 25 0 0 5 35 – – – – – – – – 20 – – –70 Min Max 70 – 60 – 60 – 0– 55 – 0– 30 – 0– 0 20 5– 55 – –100 Min Max 100 – 80 – 80 – 0– 70 – 0– 40 – 0– 0 20 5– 70 – Write waveform 1 (WE controlled) Address CS LB, UB WE tAS tWC tCW tBW tAW DIN DOUT Data undefined tWZ tAH tWP tDW tDH Data valid tOW High Z Unit Notes ns ns 12 ns ns 12 ns ns ns ns 4, 5 ns 4, 5 ns 4, 5 ns Write waveform 2 (CS controlled) Address CS LB, UB WE DIN DOUT tAS tCLZ High Z tWC tCW tAW tBW tAH tWP tWZ Data undefined tDW tDH Data valid tOW High Z 6/27/00 ALLIANCE SEMICONDUCTOR 5 5 Page

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