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PDF HT46R52A Data sheet ( Hoja de datos )
| Número de pieza | HT46R52A | |
| Descripción | (HT46R51A / HT46R52A) A/D Type 8-Bit OTP MCU | |
| Fabricantes | Holtek Semiconductor | |
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HT46R51A/HT46R52A
A/D Type 8-Bit OTP MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0004E HT48 & HT46 MCU UART Software Implementation Method
- HA0084E NiMH Battery Charger Demo Board - Using the HT46R52
Features
· Low-power fully static CMOS design
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· Program Memory:
1K´15 OTP (HT46R51A)
2K´15 OTP (HT46R52A)
· Data memory:
96´8 RAM (HT46R51A)
128´8 RAM (HT46R52A)
· A/D converter: 12bits´5Ch
External A/D converter reference voltage input pin
· 14 bidirectional I/O lines
· 1 interrupt input shared with an I/O line
· 8-bit programmable timer/event counter with over-
flow interrupt and 7-stage prescaler
· On-chip crystal and RC oscillator
· 6-level subroutine nesting
· Watchdog Timer
· Low voltage reset function
· HALT function
· Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
· 1-channel 8-bit PWM output shared with an I/O line
· PFD function
· Bit manipulation instruction
· Table read instruction
· 63 powerful instructions
· All instructions in one or two machine cycles
· 18-pin DIP, 20-pin SOP/SSOP package
General Description
The HT46R51A/HT46R52A are 8-bit high performance,
RISC architecture microcontroller devices specifically
designed for A/D applications that interface directly to
analog signals, such as those from sensors. The advan-
tages of low power consumption, I/O flexibility, timer
functions, oscillator options, multi-channel A/D con-
verter, Pulse Width Modulation function, HALT and
wake-up functions, watchdog timer, as well as low cost,
enhance the versatility of these devices to suit a wide
range of A/D application possibilities such as sensor
signal processing, chargers, motor driving, industrial
control, consumer products, subsystem controllers, etc.
Rev. 1.00
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HT46R51A/HT46R52A
Functional Description
Execution Flow
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of 4 system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch and decoding takes an instruction cy-
cle while execution take the next instruction cycle. The
pipelining scheme causes each instruction to effectively
execute in a cycle. If an instruction changes the program
counter, two cycles are required to complete the instruc-
tion.
Program Counter - PC
For HT46R52A, the program counter (PC) is 11 bits
wide and controls the sequence in which the instructions
stored in the program ROM are executed. The contents
of the PC can specify a maximum of 2048 addresses.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading register, subroutine call or return from
subroutine, initial reset, internal interrupt, external inter-
rupt or return from interrupts, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
For HT46R51A, the program counter (PC) is 10 bits
wide and controls the sequence in which the instructions
stored in the program ROM are executed. The contents
of the PC can specify a maximum of 1024 addresses.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed to the next instruction.
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
S y s te m C lo c k
O S C 2 ( R C o n ly )
PC PC
PC +1
PC +2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Initial Reset
External Interrupt
Timer/Event Counter Overflow
A/D Converter Interrupt
Skip
Loading PCL
Jump, Call Branch
Return from Subroutine
Program Counter
*b10 *b9 *b8 *b7 *b6 *b5 *b4 *b3 *b2 *b1 *b0
00000000000
00000000100
00000001000
00000001100
Program Counter+2
PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0
#10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Program Counter
Note:
*b10~*b0: Program counter bits
S10~S0: Stack register bits
#10~#0: Instruction code bits
@7~@0: PCL bits, PC10~PC8: Original PC counter, remain unchanged
For the HT46R51A, since the program counter is 10 bits wide (b0~b9), the b10 columns in the table are not ap-
plicable.
For the HT46R52A, since the program counter is 11 bits wide (b0~b10)
Rev. 1.00
5 August 24, 2006
DataSheet4 U .com
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HT46R51A/HT46R52A
C L R W D T 1 F la g
C L R W D T 2 F la g
1 o r 2 In s tr u c tio n s
C o n tro l
L o g ic
fS Y S /4
W D T O s c illa to r
W D T S o u rc e
C o n fig u r a tio n
fS 8 - b it C o u n te r fS /2 8
7 - b it C o u n te r
O p tio n
Watchdog Timer
C LR
¸2
W D T T im e - o u t
(2 15/fS ~ 2 16/fS )
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. If the
device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit TO. Whereas in the
HALT mode, the overflow will initialize a ²warm reset²
wherein only the Program Counter and SP are reset to
zero. To clear the contents of the WDT, three methods
are adopted; external reset (a low level to RES), soft-
ware instructions, or a HALT instruction. The software
instructions include ²CLR WDT² and the other set CLR
WDT1 and CLR WDT2. Of these two types of instruc-
tion, only one can be active depending on the option -
²CLR WDT times selection option². If the ²CLR WDT² is
selected (i.e. CLRWDT times equal one), any execution
of the CLR WDT instruction will clear the WDT. In case
²CLR WDT1² and ²CLR WDT2² are chosen (i.e.
CLRWDT times equal two), these two instructions must
be executed to clear the WDT; otherwise, the WDT may
reset the chip because of time-out.
The WDT time-out period is fixed to fs/216, because the
²CLR WDT² or ²CLR WDT1² and ²CLR WDT2²
instructions will clear the whole counter of the WDT.
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
· The system oscillator is turned off but the WDT oscil-
lator keeps running (if the WDT oscillator or the real
time clock is selected).
· The contents of the on-chip RAM and registers remain
unchanged
· The WDT and WDT prescaler will be cleared to zero. If
the WDT clock source is from the RTC/WDT oscilla-
tor, the WDT will remain active, and if the WDT clock
source is fSYS/4, the WDT will stop running.
· All of the I/O ports maintain their original status
· The PDF flag is set and the TO flag is cleared
The system quits the HALT mode by way of an external
reset, an interrupt, an external falling edge signal on port
A or a WDT overflow. An external reset causes a device
initialization and the WDT overflow performs a ²warm
reset². After examining the TO and PDF flags, the cause
for a chip reset can be determined. The PDF flag is
cleared by system power-up or by executing the ²CLR
WDT² instruction and is set when executing the ²HALT²
instruction. On the other hand, the TO flag is set if the
WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and SP, and leaves the oth-
ers in their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by options. Awakening from an I/O port stimulus,
the program resumes execution of the next instruction.
On the other hand, awakening from an interrupt, two se-
quence may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
resumes execution at the next instruction. But if the in-
terrupt is enabled, and the stack is not full, the regular in-
terrupt response takes place. When an interrupt request
flag is set before entering the ²HALT² status, the system
cannot be awakened using that interrupt. If wake-up
events occur, it takes 1024 tSYS (system clock period) to
resume normal operation. In other words, a dummy pe-
riod is inserted after the wake-up. If the wake-up results
from an interrupt acknowledgment, the actual interrupt
subroutine execution is delayed by more than one cycle.
However, if the Wake-up results in the next instruction
execution, the execution will be performed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset may occur:
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a ²warm reset² that
resets only the Program Counter and SP, leaving the
other circuits at their original state. Some registers re-
main unaffected during any other reset conditions. Most
registers are reset to the ²initial condition² when the re-
Rev. 1.00
11 August 24, 2006
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| PDF Descargar | [ Datasheet HT46R52A.PDF ] | |
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