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PDF HT49R50A-1 Data sheet ( Hoja de datos )
| Número de pieza | HT49R50A-1 | |
| Descripción | LCD Type 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor | |
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HT49R50A-1/HT49C50-1/HT49C50L
LCD Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0017E Controlling the Read/Write Function of the HT24 Series EEPROM Using the HT49 Series MCUs
- HA0024E Using the RTC in the HT49 MCU Series
- HA0025E Using the Time Base in the HT49 MCU Series
- HA0026E Using the I/O Ports on the HT49 MCU Series
- HA0027E Using the Timer/Event Counter in the HT49 MCU Series
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V for HT49R50A-1/HT49C50-1
fSYS=8MHz: 3.3V~5.5V for HT49R50A-1/HT49C50-1
fSYS=500kHz: 1.2V~2.2V for HT49C50L
· 8 input lines
· 12 bidirectional I/O lines
· Two external interrupt input
· Two 8-bit programmable timer/event counter with
PFD (programmable frequency divider) function
· LCD driver with 33´2, 33´3 or 32´4 segments
· 4K´15 program memory
· 160´8 data memory RAM
· Real Time Clock (RTC)
· 8-bit prescaler for RTC
· Watchdog Timer
· Buzzer output
· On-chip crystal, RC and 32768Hz crystal oscillator
· HALT function and wake-up feature reduce power
consumption
· 6-level subroutine nesting
· Bit manipulation instruction
· 15-bit table read instruction
· Up to 0.5ms instruction cycle with 8MHz system clock
for HT49R50A-1/HT49C50-1
· Up to 8ms instruction cycle with 500kHz system clock
for HT49C50L
· 63 powerful instructions
· All instructions in 1 or 2 machine cycles
· Low voltage reset/detector function
for HT49R50A-1/HT49C50-1
· 48-pin SSOP, 100-pin QFP package
General Description
The HT49R50A-1/HT49C50-1/HT49C50L are 8-bit,
high performance, RISC architecture microcontroller
devices specifically designed for a wide range of LCD
applications. The mask version HT49C50-1 and
HT49C50L are fully pin and functionally compatible with
the OTP version HT49R50A-1 device. The HT49C50L
is a low voltage version, with the ability to operate at a
minimum power supply of 1.2V, making it suitable for
single cell battery applications.
The advantages of low power consumption, I/O flexibil-
ity, programmable frequency divider, timer functions,
oscillator options, HALT and wake-up functions and
buzzer driver in addition to a flexible and configurable
LCD interface, enhance the versatility of these devices
to control a wide range of LCD-based application possi-
bilities such as measuring scales, electronic multi-
meters, gas meters, timers, calculators, remote
controllers and many other LCD-based industrial and
home appliance applications.
Rev. 2.10
1 April 24, 2006
1 page  
HT49R50A-1/HT49C50-1/HT49C50L
D.C. Characteristics
VDD=1.5V for HT49C50L, VDD=3V & VDD=5V for HT49R50A-1 and HT49C50-1
Ta=25°C
Symbol
Parameter
VDD Operating Voltage
VLCD LCD Power Supply (Note *)
IDD1
Operating Current
(Crystal OSC)
IDD2
Operating Current
(RC OSC)
IDD3
Operating Current
(Crystal OSC, RC OSC)
IDD4
Operating Current
(fSYS=RTC OSC)
ISTB1
Standby Current
(*fS=T1)
ISTB2
Standby Current
(*fS=RTC OSC)
ISTB3
Standby Current
(*fS=WDT RC OSC)
ISTB4
ISTB5
ISTB6
ISTB7
VIL1
Standby Current
(*fS=RTC OSC)
Standby Current
(*fS=RTC OSC)
Standby Current
(*fS=WDT RC OSC)
Standby Current
(*fS=WDT RC OSC)
Input Low Voltage for I/O
Ports, TMR and INT
Test Conditions
VDD Conditions
For HT49C50L
LVR disable, fSYS=4MHz
¾ (for HT49R50A-1/HT49C50-1)
fSYS=8MHz
(for HT49R50A-1/HT49C50-1)
For HT49R50A-1/HT49C50-1,
¾ VA£5.5V
1.5V No load, fSYS=455kHz
3V
No load, fSYS=4MHz
5V
1.5V No load, fSYS=400kHz
3V
No load, fSYS=4MHz
5V
Min. Typ. Max. Unit
1.2 ¾ 2.2
2.2 ¾ 5.5
V
V
3.3 ¾ 5.5 V
2.2 ¾ 5.5 V
¾ 60 100 mA
¾1
2 mA
¾3
5 mA
¾ 50 100 mA
¾1
2 mA
¾3
5 mA
5V No load, fSYS=8MHz
¾4
8 mA
1.5V
¾ 2.5 5 mA
3V No load
¾ 0.3 0.6 mA
5V ¾ 0.6 1 mA
1.5V
3V
No load, system HALT,
LCD off at HALT
5V
¾ 0.1 0.5 mA
¾ ¾ 1 mA
¾ ¾ 2 mA
1.5V
3V
No load, system HALT,
LCD On at HALT, C type
5V
¾1
2 mA
¾ 2.5 5 mA
¾ 10 20 mA
1.5V
3V
No load, system HALT
LCD On at HALT, C type
5V
¾ 0.5 1 mA
¾2
5 mA
¾ 6 10 mA
3V No load, system HALT,
¾ 17 30 mA
5V LCD on at HALT, R type, 1/2 bias ¾ 34 60 mA
3V No load, system HALT,
¾ 13 25 mA
5V LCD on at HALT, R type, 1/3 bias ¾ 26 50 mA
3V No load, system HALT,
¾ 14 25 mA
5V LCD on at HALT, R type, 1/2 bias ¾ 28 50 mA
3V No load, system HALT,
¾ 10 20 mA
5V LCD on at HALT, R type, 1/3 bias ¾ 20 40 mA
¾¾
0 ¾ 0.3VDD V
Rev. 2.10
5 April 24, 2006
5 Page 
HT49R50A-1/HT49C50-1/HT49C50L
Accumulator - ACC
The accumulator (ACC) is related to the ALU opera-
tions. It is also mapped to location 05H of the RAM and
is capable of operating with immediate data. The data
movement between two data memory locations must
pass through the ACC.
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic opera-
tions and provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data operation but
also changes the status register.
Status Register - STATUS
The status register (0AH) is of 8 bits wide and contains,
a carry flag (C), an auxiliary carry flag (AC), a zero flag
(Z), an overflow flag (OV), a power down flag (PDF), and
a watchdog time-out flag (TO). It also records the status
information and controls the operation sequence.
Except the TO and PDF flags, bits in the status register
can be altered by instructions similar to other registers.
Data written into the status register does not alter the TO
or PDF flags. Operations related to the status register,
however, may yield different results from those in-
tended. The TO and PDF flags can only be changed by
a Watchdog Timer overflow, chip power-up, or clearing
the Watchdog Timer and executing the ²HALT² instruc-
tion. The Z, OV, AC, and C flags reflect the status of the
latest operations.
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automati-
cally pushed onto the stack. If the contents of the status
is important, and if the subroutine is likely to corrupt the
status register, the programmer should take precautions
and save it properly.
Interrupts
The devices provides two external interrupts, two inter-
nal timer/event counter interrupts, an internal time base
interrupt, and an internal real time clock interrupt. The
interrupt control register 0 (INTC0;0BH) and interrupt
control register 1 (INTC1;1EH) both contain the interrupt
control bits that are used to set the enable/disable status
and interrupt request flags.
Once an interrupt subroutine is serviced, other inter-
rupts are all blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may take place during this interval,
but only the interrupt request flag will be recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 or of INTC1 may be set in order to allow interrupt
nesting. Once the stack is full, the interrupt request will
not be acknowledged, even if the related interrupt is en-
abled, until the SP is decremented. If immediate service
is desired, the stack should be prevented from becom-
ing full.
All these interrupts can support a wake-up function. As
an interrupt is serviced, a control transfer occurs by
pushing the contents of the program counter onto the
stack followed by a branch to a subroutine at the speci-
fied location in the ROM. Only the contents of the pro-
gram counter is pushed onto the stack. If the contents of
the register or of the status register (STATUS) is altered
by the interrupt service program which corrupts the de-
sired control sequence, the contents should be saved in
advance.
Bit No.
0
1
2
3
4
5
6, 7
Label
C
AC
Z
OV
PDF
TO
¾
Function
C is set if the operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-
tate through carry instruction.
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is
set by executing the ²HALT² instruction.
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO
is set by a WDT time-out.
Unused bit, read as ²0²
Status (0AH) Register
Rev. 2.10
11 April 24, 2006
11 Page | ||
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| PDF Descargar | [ Datasheet HT49R50A-1.PDF ] | |
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