|
|
PDF HT49R70A-1 Data sheet ( Hoja de datos )
| Número de pieza | HT49R70A-1 | |
| Descripción | LCD Type 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HT49R70A-1 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
HT49R70A-1/HT49C70-1/HT49C70L
LCD Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0017E Controlling the Read/Write Function of the HT24 Series EEPROM Using the HT49 Series MCUs
- HA0024E Using the RTC in the HT49 MCU Series
- HA0025E Using the Time Base in the HT49 MCU Series
- HA0026E Using the I/O Ports on the HT49 MCU Series
- HA0027E Using the Timer/Event Counter in the HT49 MCU Series
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V for HT49R70A-1/HT49C70-1
fSYS=8MHz: 3.3V~5.5V for HT49R70A-1/HT49C70-1
fSYS=500kHz: 1.2V~2.2V for HT49C70L
· 8 input lines
· 16 bidirectional I/O lines
· Two external interrupt input
· One 8-bit and one 16-bit programmable timer/event
counter with PFD (programmable frequency divider)
function
· LCD driver with 41´2, 41´3 or 40´4 segments
· 8K´16 program memory
· 224´8 data memory RAM
· Real Time Clock (RTC)
· 8-bit prescaler for RTC
· Watchdog Timer
· Buzzer output
· On-chip crystal, RC and 32768Hz crystal oscillator
· HALT function and wake-up feature reduce power
consumption
· 16-level subroutine nesting
· Bit manipulation instruction
· 16-bit table read instruction
· Up to 0.5ms instruction cycle with 8MHz system clock
for HT49R70A-1/HT49C70-1
· Up to 8ms instruction cycle with 500kHz system clock
for HT49C70L
· 63 powerful instructions
· All instructions in 1 or 2 machine cycles
· Low voltage reset/detector functions for
HT49R70A-1/HT49C70-1
· 100-pin QFP package
General Description
The HT49R70A-1/HT49C70-1/HT49C70L are 8-bit,
high performance, RISC architecture microcontroller
devices specifically designed for a wide range of LCD
applications. The mask version HT49C70-1 and
HT49C70L are fully pin and functionally compatible with
the OTP version HT49R70A-1 device. The HT49C70L
is a low voltage version, with the ability to operate at a
minimum power supply of 1.2V, making it suitable for
single cell battery applications.
The advantages of low power consumption, I/O flexibil-
ity, programmable frequency divider, timer functions,
oscillator options, HALT and wake-up functions and
buzzer driver in addition to a flexible and configurable
LCD interface, enhance the versatility of these devices
to control a wide range of LCD-based application possi-
bilities such as measuring scales, electronic multi-
meters, gas meters, timers, calculators, remote
controllers and many other LCD-based industrial and
home appliance applications.
Rev. 2.00
1 April 24, 2006
1 page  
HT49R70A-1/HT49C70-1/HT49C70L
D.C. Characteristics
VDD=1.5V for HT49C70L, VDD=3V & VDD=5V for HT49R70A-1 and HT49C70-1
Symbol
Parameter
VDD Operating Voltage
VLCD LCD Power Supply (Note *)
IDD1
Operating Current
(Crystal OSC)
IDD2
Operating Current
(RC OSC)
IDD3
Operating Current
(Crystal OSC, RC OSC)
IDD4
Operating Current
(fSYS=RTC OSC)
Test Conditions
VDD Conditions
For HT49C70L
LVR disable, fSYS=4MHz
¾ (for HT49R70A-1/HT49C70-1)
fSYS=8MHz
(for HT49R70A-1/HT49C70-1)
For HT49R70A-1/HT49C70-1,
¾ VA£5.5V
1.5V No load, fSYS=455kHz
3V
No load, fSYS=4MHz
5V
1.5V No load, fSYS=400kHz
3V
No load, fSYS=4MHz
5V
5V No load, fSYS=8MHz
1.5V
3V No load
5V
ISTB1
Standby Current
(*fS=T1)
1.5V
3V
No load, system HALT,
LCD Off at HALT
5V
ISTB2
Standby Current
(*fS=RTC OSC)
1.5V
3V
No load, system HALT,
LCD On at HALT, C type
5V
ISTB3
Standby Current
(*fS=WDT RC OSC)
1.5V
3V
No load, system HALT
LCD On at HALT, C type
5V
ISTB4
Standby Current
(*fS=RTC OSC)
3V No load, system HALT,
5V LCD On at HALT, R type, 1/2 bias
ISTB5
Standby Current
(*fS=RTC OSC)
3V No load, system HALT,
5V LCD On at HALT, R type, 1/3 bias
ISTB6
Standby Current
(*fS=WDT RC OSC)
3V No load, system HALT,
5V LCD On at HALT, R type, 1/2 bias
ISTB7
VIL1
Standby Current
(*fS=WDT RC OSC)
Input Low Voltage for I/O
Ports, TMR and INT
3V No load, system HALT,
5V LCD On at HALT, R type, 1/3 bias
¾¾
Min.
1.2
2.2
3.3
2.2
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
0
Ta=25°C
Typ. Max. Unit
¾ 2.2
¾ 5.5
V
V
¾ 5.5 V
¾ 5.5 V
60 100 mA
1 2 mA
3 5 mA
50 100 mA
1 2 mA
3 5 mA
4 8 mA
2.5 5 mA
0.3 0.6 mA
0.6 1 mA
0.1 0.5 mA
¾ 1 mA
¾ 2 mA
1 2 mA
2.5 5 mA
10 20 mA
0.5 1 mA
2 5 mA
6 10 mA
17 30 mA
34 60 mA
13 25 mA
26 50 mA
14 25 mA
28 50 mA
10 20 mA
20 40 mA
¾ 0.3VDD V
Rev. 2.00
5 April 24, 2006
5 Page 
HT49R70A-1/HT49C70-1/HT49C70L
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic opera-
tions and provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
The status register (0AH) is 8 bits wide and contains, a
carry flag (C), an auxiliary carry flag (AC), a zero flag (Z),
an overflow flag (OV), a power down flag (PDF), and a
watchdog time-out flag (TO). It also records the status
information and controls the operation sequence.
Except for the TO and PDF flags, bits in the status reg-
ister can be altered by instructions similar to other reg-
isters. Data written into the status register does not alter
the TO or PDF flags. Operations related to the status
register, however, may yield different results from those
intended. The TO and PDF flags can only be changed
by a Watchdog Timer overflow, chip power-up, or clear-
ing the Watchdog Timer and executing the ²HALT² in-
struction. The Z, OV, AC, and C flags reflect the status of
the latest operations.
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automati-
cally pushed onto the stack. If the contents of the status
is important, and if the subroutine is likely to corrupt the
status register, the programmer should take precautions
and save it properly.
Interrupts
The device provides two external interrupts, two internal
timer/event counter interrupts, an internal time base in-
terrupt, and an internal real time clock interrupt. The in-
terrupt control register 0 (INTC0;0BH) and interrupt
control register 1 (INTC1;1EH) both contain the interrupt
control bits that are used to set the enable/disable status
and interrupt request flags.
Once an interrupt subroutine is serviced, other inter-
rupts are all blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may take place during this interval,
but only the interrupt request flag will be recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 or of INTC1 may be set in order to allow interrupt
nesting. Once the stack is full, the interrupt request will
not be acknowledged, even if the related interrupt is en-
abled, until the SP is decremented. If immediate service
is desired, the stack should be prevented from becom-
ing full.
All these interrupts can support a wake-up function. As an
interrupt is serviced, a control transfer occurs by pushing
the contents of the program counter onto the stack fol-
lowed by a branch to a subroutine at the specified location
in the ROM. Only the contents of the program counter is
pushed onto the stack. If the contents of the register or of
the status register (STATUS) is altered by the interrupt ser-
vice program which corrupts the desired control sequence,
the contents should be saved in advance.
External interrupts are triggered by a high to low transi-
tion of INT0 or INT1, and the related interrupt request
flag (EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as
well. After the interrupt is enabled, the stack is not full,
and the external interrupt is active, a subroutine call to
location 04H or 08H occurs. The interrupt request flag
(EIF0 or EIF1) and EMI bits are all cleared to disable
other interrupts.
Bit No.
0
1
2
3
4
5
6, 7
Label
C
AC
Z
OV
PDF
TO
¾
Function
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-
tate through carry instruction.
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is
set by executing the ²HALT² instruction.
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO
is set by a WDT time-out.
Unused bit, read as ²0²
Status (0AH) Register
Rev. 2.00
11 April 24, 2006
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT49R70A-1.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HT49R70A-1 | LCD Type 8-Bit MCU | Holtek Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |