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PDF TMP92C820FG Data sheet ( Hoja de datos )
| Número de pieza | TMP92C820FG | |
| Descripción | 16-Bit Microcontroller | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/H1 Series
TMP92C820FG
DataSheet4 U .com
Semiconductor Company
1 page  
www.DataSheet4U.com
TMP92C820
(19) Input/output ports: 83 pins (Except Data bus (16bit), Address bus (24bit) and RD pin)
(20) Standby function
• Three HALT modes: IDLE2 (Programmable), IDLE1, STOP
(21) Triple-clock controller
• Clock gear function: Select a high-frequency clock fc to fc/16
• RTC (fs = 32.768 kHz)
(22) Operating voltage
• DVCC = 3.0 to 3.6 V
• RTCVCC = 2.0 to 3.6 V
(23) Package
• 144-pin QFP (P-LQFP144-1616-0.40C)
• Chip form supply also available. For details, contact your local Toshiba sales
representative
DataSheet4 U .com
92C820-3
2006-09-15
5 Page 
www.DataSheet4U.com
TMP92C820
Table 2.3.1 Pin Names and Functions (3/3)
Pin
Names
Number
Pins
of
I/O
Functions
PJ0
SDRAS
PJ1
SDCAS
PJ2
SDWE
SRWR
PJ3
SDLLDQM
SRLLB
PJ4
SDLUDQM
SRLUB
PJ5
SDULDQM
SRULB
PJ6
SDUUDQM
SRUUB
PJ7
SDCKE
PK0
D1BSCP
PK1
D2BLP
PK2
D3BFR
PK3
DLEBCD
PK4
DOFFB
PK6
ALARM
MLDALM
PL0 to PL7
LD0 to LD7
BE
AM0, AM1
X1/X2
XT1/XT2
RESET
VREFH
VREFL
AVCC
AVSS
DVCC
DVSS
RTCVCC
Output Port J0: Output port
1
Output Row address strobe for SDRAM: Outputs “0” when address is within SDRAM address area.
Output Port J1: Output port
1 Output Column address strobe for SDRAM: Outputs “0” when address is within SDRAM address
area.
Output Port J2: Output port
1 Output Write enable for SDRAM .
Output Write for SRAM: Strobe signal for writing data .
Output Port J3: Output port
1 Output Data enable for SDRAM on pins D0 to D7.
Output Data enable for SRAM on pins D0 to D7.
Output Port J4: Output port
1 Output Data enable for SDRAM on pins D8 to D15.
Output Data enable for SRAM on pins D8 to D15.
Output Port J5: Output port
1 Output Data enable for SDRAM on pins D16 to D23.
Output Data enable for SRAM on pins D16 to D23.
Output Port J6: Output port
1 Output Data enable for SDRAM on pins D24 to D32.
Output Data enable for SRAM on pins D24 to D32.
Output Port J7: Output port
1
Output Clock enable for SDRAM.
Output Port K0: Output port
1
Output LCD driver output pin.
Output Port K1: Output port
1
Output LCD driver output pin.
Output Port K2: Output port
1
Output LCD driver output pin.
Output Port K3: Output port
1
Output LCD driver output pin.
Output Port K4: Output port
1
Output LCD driver output pin.
Output Port K6: Output port
1 Output RTC alarm output pin.
Output Melody/alarm output pin (Inverted).
I/O Port L0 to L7: I/O port
8
Output Data bus for LCD driver.
1 Input Backup enable.
Operation mode:
2 Input Fix to AM1 = “0”, AM0 = “1”: 16-bit external bus or 8-/16-/32-bit dynamic sizing.
Fix to AM1 = “1”, AM0 = “0”: 32-bit external bus or 8-/16-/32-bit dynamic sizing.
2 I/O High-frequency oscillator connection pins.
2 I/O Low-frequency oscillator connection pins.
1 Input Reset: Initializes TMP92C820 (with pull-up resistor).
1 Input Pin for reference voltage input to AD converter (H).
1 Input Pin for reference voltage input to AD converter (L).
1 − Power supply pin for AD converter.
1 − GND pin for AD converter (0 V).
3 − Power supply pins (All DVCC pins should be connected with the power supply pin).
4 − GND pins (0 V) (All DVSS pins should be connected with GND (0V)).
1 − Power supply pin for RTC and low-frequency oscillator.
DataSheet4 U .com
92C820-9
2006-09-15
11 Page | ||
| Páginas | Total 36 Páginas | |
| PDF Descargar | [ Datasheet TMP92C820FG.PDF ] | |
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