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PDF NT7502 Data sheet ( Hoja de datos )
| Número de pieza | NT7502 | |
| Descripción | 65 X 132 RAM-Map LCD Controller / Driver | |
| Fabricantes | Novatek | |
| Logotipo |  |
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NT7502
65 X 132 RAM-Map LCD Controller / Driver
Features
! Direct RAM data display using the display RAM. When
RAM data bit is 0, it is not displayed. When RAM data bit
is 1, it is displayed. (At normal display)
! RAM capacity: 65 X 132 = 8580 bits
! Many command functions: Read/Write Display Data.
Display ON/OFF. Normal/Reverse Display. Page
Address Set. Set Display Start Line. Set LCD Bias,
Electronic contrast Controls, V0 voltage regulation
internal resistor ratio set, Read Modify Write, Select
Segment Driver Direction, Power Save
General Description
The NT7502 is a single-chip LCD driver for dot-matrix liquid
crystal displays which is directly connectable to a
microcomputer bus. It accepts 8-bit serial or parallel display
data directly sent from a microcomputer and stores it in an
on-chip display RAM. It generates a LCD drive signal
independent of the microprocessor clock.
The set of the on-chip display RAM of 65 X 132 bits and a
one-to-one correspondence between LCD panel pixel dots
and on-chip RAM bits permit implementation of displays with
a high degree of freedom.
Pin Configuration
! High-speed 8-bit microprocessor interface allowing direct
connection to both the 8080 and 6800
! Serial interface
! Power supply voltage: 2.4 - 3.5V
! Maximum 12V LCD driving output voltage
! 2X / 3X / 4X on chip DC-DC converter
! Voltage regulator
! Voltage follower
! On-chip oscillator
The NT7502 contains 65 common output circuits and 132
segment output circuits, so that a single chip of NT7502 can
make 65 X 132, 55 X 132, 49 X 132 and 33 X 132 dot
displays with pad option (DUTY1, DUTY0).
No external operation clock is required for RAM read/write
operations. Accordingly, this driver can be operated with a
minimum current consumption and its onboard
low-current-consumption liquid crystal power supply can
implement a high-performance handy display system with
minimum current consumption and the smallest LSI
configuration.
NT7502H-TABF1
(Copper Side View)
1 V1.0
1 page  
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LCD Driver Supplies
Pad No.
45 - 46
47 - 48
51 - 52
49 - 50
43 - 44
41 - 42
Symbol
CAP1-
CAP1+
CAP2-
CAP2+
CAP3+
VOUT
67 - 68
VR
54 VEXT
82 TMPS
55 VRS
NT7502
I/O Descriptions
O Capacitor 1- pad for internal DC/DC voltage converter
O Capacitor 1+ pad for internal DC/DC voltage converter
O Capacitor 2- pad for internal DC/DC voltage converter
O Capacitor 2+ pad for internal DC/DC voltage converter
O Capacitor 3+ pad for internal DC/DC voltage converter
O DC/DC voltage converter output
I
Voltage adjustment pad. Applies voltage between V0 and VSS using a
resistive divider
This is the external input reference voltage (VREF) for the internal
I
voltage regulator. It is valid only when external VREF is used.
VEXT must be ≥ 2.4V and ≤ VDD2
When using internal VREF, this pad must be NC
Selects temperature coefficient of the reference voltage
I TMPS = 0: -0.05% / °C
TMPS = 1: -0.2 % / °C
Select the internal voltage regulator or external voltage regulator,
I VRS = 0: using the external VREF
VRS = 1: using the internal VREF
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NT7502
MPU
A0
E
R/W
DATA
Address preset
Read signal
Internal
timing
Column address
NN n
Preset
N
Incremented
N+1
n+1
N+2
BUS holder
N
Set address n Dummy read
n n+1 n+2
Data Read address n Data Read address n+1
Figure. 2
Busy Flag
When the busy flag is “1”, it indicates that the NT7502 chip is running internal processes, and at this time no command aside
from a status read will be received. The busy flag is outputted to D7 pad with the read instruction. If the cycle time (tCYC) is
maintained, it is not necessary to check for this flag before each command. This makes vast improvements in MPU processing
capabilities possible.
Display Data RAM
Display Data RAM
The display data RAM is RAM that stores the dot data for the display. It has a 65 (8 page * 8 bit+1)*132 bit structure. It is
possible to access the desired bit by specifying the page address and the column address. Because, as is shown in Figure3,
the D7 to D0 display data from the MPU corresponds to the liquid crystal display common direction, there are few constraints at
the time of display common direction, and there are few constraints at the time of display data transfer when multiple NT7502
chips are used, thus display structures with a high degree of freedom can be created easily .
Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an
independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed
asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering).
D0 0 1 1 1
D1 1 0 0 0
D2 0 0 0 0
D3 0 1 1 1
D4 1 0 0 0
0
0
0
0
0
COM0
COM1
COM2
COM3
COM4
Display data RAM
Figure. 3
Display on LCD
11
11 Page | ||
| Páginas | Total 54 Páginas | |
| PDF Descargar | [ Datasheet NT7502.PDF ] | |
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