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PDF DS33R11 Data sheet ( Hoja de datos )
| Número de pieza | DS33R11 | |
| Descripción | Ethernet Mapper | |
| Fabricantes | Maxim Integrated Products | |
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DS33R11
Ethernet Mapper with Integrated
T1/E1/J1 Transceiver
GENERAL DESCRIPTION
The DS33R11 extends a 10/100 Ethernet LAN
segment by encapsulating MAC frames in HDLC or
X.86 (LAPS) for transmission over a T1/E1/J1 data
stream.
The device performs store-and-forward of packets
with full wire-speed transport capability. The built-in
Committed Information Rate (CIR) Controller
provides fractional bandwidth allocation up to the line
rate in increments of 512kbps. The DS33R11 can
operate with an inexpensive external processor.
APPLICATIONS
Transparent LAN Service
LAN Extension
Ethernet Delivery Over T1/E1/J1
FUNCTIONAL DIAGRAM
FEATURES
§ 10/100 IEEE 802.3 Ethernet MAC (MII and RMII)
Half/Full Duplex with Automatic Flow Control
§ Integrated T1/E1/J1 Framer and LIU
§ HDLC/LAPS Encapsulation with Programmable
FCS and Interframe Fill
§ Committed Information Rate Controller Provides
Fractional Allocations in 512kbps Increments
§ Programmable BERT for Serial (TDM) Interface
§ External 16MB, 100MHz SDRAM Buffering
§ Parallel Microprocessor Interface
§ 1.8V, 3.3V Supplies
§ Reference Design Routes on Two Signal Layers
§ IEEE 1149.1 JTAG Support
Features continued on page 11.
SERIAL STREAM
T1/E1/J1
TRANSCEIVER
BERT
HDLC/X.86
MAPPER
T1/E1
LINE
mC
SDRAM
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS33R11
-40°C to +85°C 256 BGA
10/100
MAC
MII/RMII
DS33R11
10/100
ETHERNET
PHY
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
12.2 MII AND RMII INTERFACES ...................................................................................................... 295
12.3 TRANSCEIVER T1 MODE FUNCTIONAL TIMING ........................................................................... 297
12.4 E1 MODE ...............................................................................................................................302
13 OPERATING PARAMETERS ..................................................................................................... 307
13.1 THERMAL CHARACTERISTICS ................................................................................................... 308
13.2 MII INTERFACE........................................................................................................................ 309
13.3 RMII INTERFACE ..................................................................................................................... 311
13.4 MDIO INTERFACE ................................................................................................................... 313
13.5 TRANSMIT WAN INTERFACE .................................................................................................... 314
13.6 RECEIVE WAN INTERFACE ...................................................................................................... 315
13.7 SDRAM TIMING...................................................................................................................... 316
13.8 MICROPROCESSOR BUS AC CHARACTERISTICS ........................................................................ 318
13.9 AC CHARACTERISTICS: RECEIVE-SIDE ..................................................................................... 321
13.10AC CHARACTERISTICS: BACKPLANE CLOCK TIMING .................................................................. 325
13.11AC CHARACTERISTICS: TRANSMIT SIDE ................................................................................... 326
13.12JTAG INTERFACE TIMING ........................................................................................................ 329
14 JTAG INFORMATION ................................................................................................................ 330
14.1 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION .......................................................... 331
14.2 INSTRUCTION REGISTER .......................................................................................................... 333
14.3 JTAG ID CODES..................................................................................................................... 335
14.4 TEST REGISTERS .................................................................................................................... 335
14.4.1 Boundary Scan Register ...................................................................................................................335
14.4.2 Bypass Register ................................................................................................................................335
14.4.3 Identification Register........................................................................................................................335
14.5 JTAG FUNCTIONAL TIMING...................................................................................................... 336
15 PACKAGE INFORMATION ........................................................................................................ 337
15.1 PACKAGE OUTLINE DRAWING OF 256-BGA (VIEW FROM BOTTOM OF DEVICE) ........................... 337
16 REVISION HISTORY.................................................................................................................. 338
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
2 FEATURE HIGHLIGHTS
2.1 General
· 256-pin, 27mm BGA package
· 1.8V and 3.3V supplies
· IEEE 1149.1 JTAG boundary scan
· Software access to device ID and silicon revision
· Development support includes evaluation kit, driver source code, and reference designs
· Reference design routes on a two-layer PC board
· Programmable output clocks for fractional T1, E1, H0, and H12 applications
2.2 Microprocessor Interface
· Parallel control port with 8-bit data bus
· Nonmultiplexed Intel and Motorola timing modes
· Internal software reset and external hardware reset-input pin
· Supports polled or interrupt-driven environments
· Software access to device ID and silicon revision
· Global interrupt-output pin
2.3 HDLC Ethernet Mapping
· Dedicated HDLC controller engine for protocol encapsulation
· Compatible with polled or interrupt driven environments
· Programmable FCS insertion and extraction
· Programmable FCS type
· Supports FCS error insertion
· Programmable packet size limits (Minimum 64 bytes and maximum 2016 bytes)
· Supports bit stuffing/destuffing
· Selectable packet scrambling/descrambling (X43+1)
· Separate FCS errored packet and aborted packet counts
· Programmable inter-frame fill for transmit HDLC
2.4 X.86 (Link Access Protocol for SONET/SDH) Ethernet Mapping
· Programmable X.86 address/control fields for transmit and receive
· Programmable 2-byte protocol (SAPI) field for transmit and receive
· 32 bit FCS
· Transmit transparency processing—7E is replaced by 7D, 5E
· Transmit transparency processing—7D replaced by 7D, 5D
· Receive rate adaptation (7D, DD) is deleted.
· Receive transparency processing—7D, 5E is replaced by 7E
· Receive transparency processing—7D, 5D is replaced by 7D
· Receive abort sequence the LAPS packet is dropped if 7D7E is detect
· Self-synchronizing X43+1 payload scrambling.
· Frame indication due to bad address/control/SAPI, FCS error, abort sequence or frame size longer
than preset max
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| PDF Descargar | [ Datasheet DS33R11.PDF ] | |
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