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PDF CY7C1464AV25 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1464AV25 | |
| Descripción | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
36-Mbit (1M x 36/2M x 18/512K x 72)
Pipelined SRAM with NoBL™ Architecture
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• 2.5V core power supply
• 2.5V/1.8V I/O power supply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• CY7C1460AV25, CY7C1462AV25 available in
JEDEC-standard lead-free 100-pin TQFP package,
lead-free and non-lead-free 165-ball FBGA package.
CY7C1464AV25 available in lead-free and non-lead-free
209-ball FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are
2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back
Read/Write operations with no wait states. The
CY7C1460AV25/CY7C1462AV25/CY7C1464AV25
are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read
transitions.
The
CY7C1460AV25/CY7C1462AV25/CY7C1464AV25
are
pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle. Write operations are controlled by the
Byte Write Selects (BWa–BWh for CY7C1464AV25,
BWa–BWd for CY7C1460AV25 and BWa–BWb for
CY7C1462AV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram–CY7C1460AV25 (1M x 36)
A0, A1, A
MODE
CLK C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
BWb
BWc
BWd
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
DQs
DQPa
DQPb
DQPc
DQPd
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05354 Rev. *D
Revised June 22, 2006
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1 page  
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Pin Configurations (continued)
209-ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1464AV25 (512K x 72)
12345678
9
10 11
A DQg DQg
A
CE2 A ADV/LD A
CE3
A
DQb
DQb
B DQg DQg BWSc BWSg NC WE
A BWSb BWSf DQb DQb
C DQg DQg BWSh BWSd NC/576M CE1
NC BWSe BWSa DQb DQb
D DQg DQg VSS NC NC/1G OE
NC NC VSS DQb DQb
E DQPg DQPc VDDQ VDDQ VDD
VDD
VDD
VDDQ VDDQ DQPf DQPb
F
DQc
DQc
VSS
VSS
VSS NC
VSS
VSS
VSS
DQf DQf
G
DQc
DQc
VDDQ VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQf
DQf
H
DQc
DQc
VSS
VSS
VSS NC
VSS
VSS
VSS
DQf DQf
J
DQc
DQc
VDDQ VDDQ
VDD
NC
VDD
VDDQ VDDQ
DQf
DQf
K NC NC CLK NC VSS CEN VSS NC NC NC NC
L
DQh
DQh VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQa
DQa
M
DQh
DQh VSS
VSS
VSS NC
VSS
VSS
VSS
DQa DQa
N
DQh
DQh VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQa
DQa
P
DQh DQh VSS
VSS
VSS ZZ
VSS
VSS
VSS
DQa DQa
R
DQPd DQPh VDDQ VDDQ
VDD
VDD
VDD
VDDQ
VDDQ DQPa DQPe
T
DQd DQd VSS
NC
NC MODE NC
NC VSS
DQe DQe
U DQd DQd NC/144M A NC/72M A
A
A NC/288M DQe DQe
V
DQd DQd
A
A
A A1 A A
A DQe DQe
W
DQd DQd TMS
TDI
A
A0
A
TDO
TCK
DQe DQe
Pin Definitions
Pin Name
A0
A1
A
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
WE
ADV/LD
CLK
I/O Type
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Clock
Pin Description
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,
BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf
controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Document #: 38-05354 Rev. *D
Page 5 of 27
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5 Page 
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The length of the Boundary
Scan Register for the SRAM in different packages is listed in
the Scan Register Sizes table.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1-mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #89
(for 165-FBGA package) or bit #138 (for 209 FBGA package).
Document #: 38-05354 Rev. *D
Page 11 of 27
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| PDF Descargar | [ Datasheet CY7C1464AV25.PDF ] | |
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