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PDF MB15F78UL Data sheet ( Hoja de datos )

Número de pieza MB15F78UL
Descripción Dual Serial Input PLL Frequency Synthesizer
Fabricantes Fujitsu Media Devices 
Logotipo Fujitsu Media Devices Logotipo



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FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21369-1E
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F78UL
s DESCRIPTION
The Fujitsu MB15F78UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2600 MHz and
a 1200 MHz prescalers. A 32/33 or a 64/65 for the 2600 MHz prescaler, and a 16/17 or a 32/33 for the 1200 MHz
prescaler can be selected for the prescaler that enables pulse swallow operation.
The BiCMOS process is used, as a result a supply current is typically 4.5 mA at 2.7 V. The supply voltage range
is from 2.4 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA
selectable by serial date. The data format is the same as the previous one MB15F08SL, MB15F78SP. Fast locking
is achieved for adopting the new circuit.
The new package (BCC20) decreases a mount area of MB15F78UL more than 30% comparing with the former
BCC16 (for dual PLL) .
MB15F78UL is ideally suited for wireless mobile communications, such as GSM and PCS.
s FEATURES
• High frequency operation
: RX synthesizer : 2600 MHz Max.
: TX synthesizer : 1200 MHz Max.
• Low power supply voltage
: VCC = 2.4 to 3.6 V
• Ultra low power supply current : ICC = 4.5 mA Typ.
(VCC = Vp = 2.7 V, Ta = +25 °C, SWTX = SWRX = 0, in TX/RX locking state)
s PACKAGES
(Continued)
20-pin plastic TSSOP
20-pad plastic BCC
(FPT-20P-M06)
(LCC-20P-M05)

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MB15F78UL pdf
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MB15F78UL
s ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Min.
Rating
Max.
Unit
Power supply voltage
VCC 0.5
Vp VCC
4.0
4.0
V
V
Input voltage
VI
0.5
VCC + 0.5
V
Output voltage
LD/fout
DoTX, DoRX
VO
VDD
GND
GND
VCC
Vp
V
V
Storage temperature
Tstg
55
+125
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min.
Value
Typ.
Max.
Unit
Remarks
VCC 2.4 2.7 3.6 V VCCRX = VCCTX
Power supply voltage
Vp VCC 2.7 3.6 V
Input voltage
VI GND
VCC V
Operating temperature
Ta
40
+85 °C
Note : VCCRX, VpRX, VCCTX and VpTX must supply equal voltage.
Even if either RX-PLL or TX-PLL is not used, power must be supplied to VCCRX, VpRX, VCCTX and VpTX to
keep them equal.
It is recommended that the non-use PLL is controlled by power saving function.
Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry
has been improved in electrostatic protection, observe the following precautions when handling the device.
When storing and transporting the device, put it in a conductive case.
Before handling the device, confirm the (jigs and) tools to be used have been uncharged (grounded) as
well as yourself. Use a conductive sheet on working bench.
Before fitting the device into or removing it from the socket, turn the power supply off.
When handling (such as transporting) the device mounted board, protect the leads with a conductive
sheet.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
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MB15F78UL
3. Power Saving Mode (Intermittent Mode Control Circut)
Status
PSTX/PSRX pins
Normal mode
H
Power saving mode
L
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pins low, the device enters into the power saving mode, reducing the current consumption.
See the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pins high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr)
which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase
in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
Notes : When power (VCC) is first applied, the device must be in standby mode, PSTX = PSRX = Low, for at least 1 µs.
PS pins must be set at “L” at Power-ON
VCC
Clock
Data
LE
PSTX
PSRX
OFF
ON
tV 1 µs
(1) (2)
tPS 100 ns
(3)
(1) PSTX = PSRX = “L” (power saving mode) at Power-ON
(2) Set serial data at least 1 µs after the power supply becomes stable (VCC 2.2 V) .
(3) Release power saving mode (PSTX, PSRX : “L” “H”) at least 100 ns after setting serial data.
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