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PDF MB15F73SP Data sheet ( Hoja de datos )
| Número de pieza | MB15F73SP | |
| Descripción | Dual Serial Input PLL Frequency Synthesizer | |
| Fabricantes | Fujitsu Media Devices | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21365-1E
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F73SP
s DESCRIPTION
The Fujitsu MB15F73SP is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2000 MHz pres-
caler and a 600 MHz prescaler. A 64/65 or a 128/129 for the 2000 MHz prescaler, and a 8/9 or a 16/17 for the 600
MHz prescaler can be selected for the prescaler that enables pulse swallow operation.
MB15F73SP has the same configuration with MB15F03 or MB15F03L. The BiCMOS process is used , as a result
a supply current is typically 3.5 mA at 2.7 V. The supply voltage range is from 2.4 V to 3.6 V. A refined charge
pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial data.
The new package (BCC20) decreases an area of MB15F73SP more than 30 % comparing with the former BCC16
(for dual PLL).
MB15F73SP is ideally suited for wireless mobile communications, such as PDC.
s FEATURES
• High frequency operation
: RF synthesizer : 2000 MHz max
: IF synthesizer : 600 MHz max
• Low power supply voltage
: VCC = 2.4 to 3.6 V
• Ultra Low power supply current : ICC = 3.5 mA typ.
(VCC = Vp = 2.7 V, Ta = +25°C, SWIF = SWRF = 0 in IF/RF locking state)
s PACKAGES
(Continued)
20-pin plastic TSSOP
20-pad plastic BCC
(FPT-20P-M06)
(LCC-20P-M04)
1 page  
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MB15F73SP
s ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Min.
Max.
Unit
Power supply voltage
Input voltage
VCC −0.5 4.0
V
Vp VCC 4.0
V
VI
−0.5
VCC + 0.5
V
Output voltage
Storage temperature
LD/fout
Do
VO
VDO
Tstg
GND
GND
−55
VCC
Vp
+125
V
V
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter
Power supply voltage
Input voltage
Operating temperature
Symbol
VCC
Vp
VI
Ta
Min.
2.4
VCC
GND
−40
Value
Typ.
2.7
2.7
Max.
3.6
3.6
VCC
+85
Unit
V
V
V
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
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MB15F73SP
3. Power Saving Mode (Intermittent Mode Control Circuit)
Status
PS pin
Normal mode
H
Power saving mode
L
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the single PLL, the lock detector, LD, remains high, indicating a locked condition.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is be-
cause of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which
can cause a major change in the comparaor output, resulting in a VCO frequency jump and an increase in lockup
time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error sig-
nal from the phase detector when it returns to normal operation.
Note : When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1µs.
Note : PS pin must be set "L" for Power-ON.
VCC
Clock
Data
LE
PS
OFF
ON
tV ≥ 1 µs
tPS ≥ 100 ns
(1) (2)
(3)
(1) PS = L (power saving mode) at Power-ON
(2) Set serial data 1 µs later after power supply remains stable (VCC > 2.2 V).
(3) Release power saving mode (PS : L → H) 100 ns later after setting serial data.
11
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| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet MB15F73SP.PDF ] | |
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