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PDF MB15F08SL Data sheet ( Hoja de datos )
| Número de pieza | MB15F08SL | |
| Descripción | Dual Serial Input PLL Frequency Synthesizer | |
| Fabricantes | Fujitsu Media Devices | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F08SL
DS04-21362-2E
s DESCRIPTION
The Fujitsu MB15F08SL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 2500 MHz and a
1100 MHz prescalers. The 2500 MHz prescaler, and 1100 MHz prescaler have a dual modulus division ratio of 32/
33 or 64/65 and 16/17 or 32/33 enabling pulse swallow operation.
The supply voltage range is between 2.4 V and 3.6 V.
The MB15F08SL uses the latest BiCMOS process. As a result, the supply current is typically 7.0 mA at 2.7 V. A
refined charge pump supplies a well-balanced output current of 1.5 mA or 6 mA. The charge pump current is selectable
by serial data.
MB15F08SL is ideally suited for wireless mobile communications.
s FEATURES
• High frequency operation: RX synthesizer: 2500 MHz max
TX synthesizer: 1100 MHz max
• Low power supply voltage: VCC = 2.4 to 3.6 V
• Ultra Low power supply current: ICC = 7.0 mA typ. (VCC = 2.7 V, Ta = +25°C, in TX, RX locking state)
ICC = 7.5 mA typ. (VCC = 3.0 V, Ta = +25°C, in TX, RX locking state)
• Direct power saving function: Power supply current in power saving mode
Typ. 0.1 µA (VCC = 3V, Ta = +25°C), Max. 10 µA (VCC = 3V)
• Dual modulus prescaler: 2500 MHz prescaler (32/33 or 64/65)/1100 MHz prescaler (16/17 or 32/33)
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
• Software selectable charge pump current
• On–chip phase control for phase comparator
• Operating temperature: Ta = –40 to +85°C
s PACKAGES
16-pin, Plastic SSOP
16-pad, Plastic BCC
(FPT-16P-M05)
(LCC-16P-M04)
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MB15F08SL
s ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input voltage
Output voltage
Storage temperature
Symbol
VCC
VI
VO
Tstg
Rating
Min.
Max.
–0.5
+4.0
–0.5
VCC +0.5
GND
VCC
–55 +125
Unit
V
V
V
°C
Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter
Power supply voltage
Input voltage
Operating temperature
Symbol
VCC
VI
Ta
Min.
2.4
GND
–40
Value
Typ.
3.0
–
–
Max.
3.6
VCC
+85
Unit
V
V
°C
Remark
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
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MB15F08SL
Table.9 Charge Pump Current Setting
CS Current value
H ±6.0 mA
L ±1.5 mA
Power Saving Mode (Intermittent Mode Control Circuit)
Table.10 PS Pin Setting
PS pin
H
L
Status
Normal mode
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because
of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal
from the phase detector when it returns to normal operation.
Note: When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 µs.
Note: PS pin must be set “L” for Power-ON.
OFF
ON
VCC tV ≥ 1 µs
Clock
Data
LE
PS
tps ≥ 100 ns
(1) (2)
(3)
(1) PS = L (power saving mode) at Power-ON
(2) Set serial data 1 µs later after power supply remains stable (VCC > 2.2 V).
(3) Release power saving mode (PS : L → H) 100 ns later after setting serial data.
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| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet MB15F08SL.PDF ] | |
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