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PDF CY24239 Data sheet ( Hoja de datos )
| Número de pieza | CY24239 | |
| Descripción | Spread Spectrum Frequency Timing Generator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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39
CY24239
Spread Spectrum Frequency Timing Generator
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum Technology
• –1.2% and –2.4% Spread Spectrum support
• Three copies of CPU output
• Seven copies of PCI output
• One 48-MHz output for USB / One 24-MHz for SIO
• Two buffered reference outputs
• Two IOAPIC outputs
• Seventeen SDRAM outputs provide support for
4 DIMMs
• SMBus interface for programming
• Power management control inputs
Key Specifications
CPU Cycle-to-Cycle Jitter: .......................................... 250 ps
CPU to CPU Output Skew: ......................................... 350 ps
PCI to PCI Output Skew: ............................................ 500 ps
SDRAMIN to SDRAM0:16 Delay: ..........................3.7 ns typ.
VDDQ3: .................................................................... 3.3V±5%
Table 1. Mode Input Table
Mode
Pin 3
0 PCI_STOP#
1 REF0
Block Diagram
X1
X2
CLK_STOP#
XTAL
OSC
PLL Ref Freq
I/O Pin
Control
Stop
Clock
Control
PLL 1
Stop
Clock
Control
÷2,3,4
SDATA
SCLK
SMBus
Logic
Stop
Clock
Control
SDRAMIN
PLL2
Stop
Clock
Control
VDDQ3
REF0/(PCI_STOP#)
REF1/FS2
VDDQ3
IOAPIC_F
IOAPIC0
VDDQ3
CPU_F
CPU1
CPU2
VDDQ3
PCI_F/MODE
PCI0/FS3
PCI1
PCI2
PCI3
PCI4
PCI5
VDDQ3
48MHz/FS1
24MHz/FS0
VDDQ3
SDRAM0:16
17
Table 2. Pin Selectable Frequency
Input Address
CPU_F,
CPU1:2
FS3 FS2 FS1 FS0 (MHz)
1 1 1 1 91.66
1 1 1 0 75.0
1 1 0 1 100.0
1 1 0 0 83.3
1 0 1 1 66.6
1 0 1 0 105.0
1 0 0 1 110.0
1 0 0 0 133.3
0 1 1 1 91.66
0 1 1 0 75.0
0 1 0 1 100.0
0 1 0 0 83.3
0 0 1 1 91.66
0 0 1 0 75.0
0 0 0 1 100.0
0 0 0 0 83.3
PCI_F,
PCI0:5
(MHz)
30.5
25.0
33.3
27.76
33.3
26.3
27.5
33.3
30.5
25.0
33.3
27.76
30.5
25.0
33.3
27.76
Spread
Spec-
trum
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
–1.2%
–1.2%
–1.2%
–1.2%
–2.4%
–2.4%
–2.4%
–2.4%
Pin Configuration[1]
VDDQ3
REF1/FS2
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI0/FS3
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
SDRAMIN
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VDDQ3
55 IOAPIC0
54 IOAPIC_F
53 GND
52 CPU_F
51 CPU1
50 VDDQ3
49 CPU2
48 GND
47 CLK_STOP#
46 SDRAM16
45 VDDQ3
44 SDRAM0
43 SDRAM1
42 GND
41 SDRAM2
40 SDRAM3
39 SDRAM4
38 SDRAM5
37 VDDQ3
36 SDRAM6
35 SDRAM7
34 GND
33 SDRAM12
32 SDRAM13
31 VDDQ3
30 24MHz/FS0
29 48MHz/FS1
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07038 Rev. **
Revised May 18, 2001
1 page  
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CY24239
Serial Data Interface
The CY24239 features a two-pin, serial data interface that can
be used to configure internal register settings that control par-
ticular device functions. Upon power-up, the CY24239 initial-
izes with default register settings, therefore the use of this se-
rial data interface is optional. The serial interface is write-only
(to the clock chip) and is the dedicated function of device pins
SDATA and SCLOCK. In motherboard applications, SDATA
and SCLOCK are typically driven by two logic outputs of the
chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power manage-
ment functions. Table 3 summarizes the control functions of
the serial data interface.
Operation
Data is written to the CY24239 in eleven bytes of eight bits
each. Bytes are written in the order shown in Table 4.
Table 3. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Output Disable
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI
abled outputs are actively held low.
and system power. Examples are clock out-
puts to unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections alternate
to the selections that are provided by the FS0:3
pins. Frequency is changed in a smooth and con-
trolled fashion.
For alternate microprocessors and power
management options. Smooth frequency tran-
sition allows CPU frequency change under
normal system operation.
Spread Spectrum
Enabling
Enables or disables spread spectrum clocking.
For EMI reduction.
Output Three-state
Puts all clock outputs into a high-impedance state. Production PCB testing.
Test Mode
All clock outputs toggle in relation to X1 input, inter- Production PCB testing.
nal PLL is bypassed. Refer to Table 5.
(Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be writ-
duction device testing.
ten as 0.
Table 4. Byte Writing Sequence
Byte Sequence Byte Name
1 Slave Address
2 Command
Code
3 Byte Count
4 Data Byte 0
5 Data Byte 1
6 Data Byte 2
7 Data Byte 3
8 Data Byte 4
9 Data Byte 5
10 Data Byte 6
11 Data Byte 7
Bit Sequence
Byte Description
11010010
Commands the CY24239 to accept the bits in Data Bytes 0–7 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the CY24239 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Don’t Care
Unused by the CY24239, therefore bit values are ignored (“Don’t Care”).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
Don’t Care
Unused by the CY24239, therefore bit values are ignored (“Don’t Care”).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Byte Count Byte is part of the standard serial com-
munication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
Refer to Table 5
The data bits in Data Bytes 0–7 set internal CY24239 registers that
control device operation. The data bits are only accepted when the Ad-
dress Byte bit sequence is 11010010, as noted above. For description
of bit control functions, refer to Table 5, Data Byte Serial Configuration
Map.
Don’t Care
Unused by the CY24239, therefore bit values are ignored (“don’t care”).
Document #: 38-07038 Rev. **
Page 5 of 15
5 Page 
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CY24239
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
tP Period
Measured on rising edge at 1.5V
tH High Time
Duration of clock cycle above 2.4V
tL Low Time
Duration of clock cycle below 0.4V
tR Output Rise Edge Rate Measured from 0.4V to 2.4V
tF Output Fall Edge Rate Measured from 2.4V to 0.4V
tD Duty Cycle
Measured on rising and falling edge at 1.5V
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
tSK Output Skew
Measured on rising edge at 1.5V
tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
fST Frequency Stabilization Assumes full supply voltage reached within 1 ms
from Power-up (cold
from power-up. Short cycles exist prior to frequency
start)
stabilization.
Zo AC Output Impedance Average value during switching transition. Used for
determining series termination value.
Min.
30
12
12
1
1
45
1.5
Typ.
15
Max.
4
4
55
250
500
4
3
Unit
ns
ns
ns
V/ns
V/ns
%
ps
ps
ns
ms
Ω
IOAPIC0 and IOAPIC_F Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Frequency generated by crystal oscillator
tR
Output Rise Edge Rate
Measured from 0.4V to 2.0V
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
tD Duty Cycle
Measured on rising and falling edge at 1.25V
fST Frequency Stabilization from Assumes full supply voltage reached within
Power-up (cold start)
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Min.
1
1
45
Typ.
14.318
15
Max.
4
4
55
1.5
Unit
MHz
V/ns
V/ns
%
ms
Ω
REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Frequency generated by crystal oscillator
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
tD Duty Cycle
Measured on rising and falling edge at 1.5V
fST Frequency Stabilization from Assumes full supply voltage reached within
Power-up (cold start)
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Min.
0.5
0.5
45
Typ.
14.318
25
Max.
2
2
55
3
Unit
MHz
V/ns
V/ns
%
ms
Ω
Document #: 38-07038 Rev. **
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