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PDF AD9980 Data sheet ( Hoja de datos )
| Número de pieza | AD9980 | |
| Descripción | High Performance 8-Bit Display Interface | |
| Fabricantes | Analog Devices | |
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FEATURES
95 MSPS maximum conversion rate
9% or less p-p PLL clock jitter at 95 MSPS
Automated offset adjustment
2:1 input mux
Power-down via dedicated pin or serial register
4:4:4, 4:2:2, and DDR output format modes
Variable output drive strength
Odd/even field detection
External clock input
Regenerated Hsync output
Programmable output high impedance control
Hsyncs per Vsyncs counter
Pb-free package
APPLICATIONS
Advanced TVs
Plasma display panels
LCD TV
HDTV
RGB graphics processing
LCD monitors and projectors
Scan converters
GENERAL DESCRIPTION
The AD9980 is a complete, 8-bit, 95 MSPS, monolithic analog
interface optimized for capturing YPbPr video and RGB
graphics signals. Its 95 MSPS encode rate capability and full-
power analog bandwidth of 200 MHz supports all HDTV
video modes and graphics resolutions up to XGA (1024 × 768
at 85 Hz).
The AD9980 includes a 95 MHz triple ADC with an internal
reference, a phase-locked loop (PLL), programmable gain,
offset, and clamp controls. The user provides only 3.3 V and
1.8 V power supplies and an analog input. Three-state CMOS
outputs may be powered from 1.8 V to 3.3 V.
The AD9980’s on-chip PLL generates a sample clock from
the three-level sync (for YPbPr video) or the horizontal sync
(for RGB graphics). Sample clock output frequencies range from
10 MHz to 95 MHz. PLL clock jitter is 9% or less p-p typical at
95 MSPS.
High Performance
8-Bit Display Interface
AD9980
FUNCTIONAL BLOCK DIAGRAM
PR/REDIN1
PR/REDIN0
Y/GREENIN1
Y/GREENIN0
PB/BLUEIN1
PB/BLUEIN0
2:1
MUX
2:1
MUX
2:1
MUX
8 AUTO OFFSET
CLAMP
PGA
8-BIT
ADC
8
8 AUTO OFFSET
AD9980
8
CB/CR/REDOUT
CLAMP
PGA
8-BIT
ADC
8
8 AUTO OFFSET
8
Y/GREENOUT
CLAMP
PGA
8-BIT
ADC
8
8
CB/BLUEOUT
HSYNC1
HSYNC2
VSYNC1
VSYNC2
SOGIN1
SOGIN2
EXTCLK/COAST
CLAMP
FILT
SDA
SCL
2:1
MUX
2:1
MUX
2:1
MUX
SYNC
PROCESSING
PLL
POWER
MANAGEMENT
SERIAL REGISTER
Figure 1.
DTACK
SOGOUT
O/E FIELD
HSOUT
VSOUT/A0
VOLTAGE
REFS
REFHI
REFCM
REFLO
With internal Coast generation, the PLL maintains its output
frequency in the absence of sync input. A 32-step sampling
clock phase adjustment is provided. Output data, sync, and
clock phase relationships are maintained.
The auto-offset feature can be enabled to automatically restore
the signal reference levels and to automatically calibrate out any
offset differences between the three channels. The AD9980 also
offers full sync processing for composite sync and sync-on-
green applications. A clamp signal is generated internally or
may be provided by the user through the CLAMP input pin.
Fabricated in an advanced CMOS process, the AD9980 is
provided in a space-saving, 80-pin, Pb-free, LQFP surface
mount plastic package. It is specified over the 0°C to +70°C
temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
DataSheet4 U .com
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
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ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VD
VDD
PVD
DAVDD
Analog Inputs
REFHI
REFCM
REFLO
Digital Inputs
Digital Output Current
Functional Temperature
Storage Temperature
Maximum Junction Temperature
Rating
3.6 V
3.6 V
1.98 V
1.98 V
VD to 0.0 V
VD to 0.0 V
VD to 0.0 V
VD to 0.0 V
5 V to 0.0 V
20 mA
−25°C to + 85°C
−65°C to + 150°C
150°C
AD9980
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
DataSheet4 U .com
Rev. 0 | Page 5 of 44
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AD9980
In most PC graphics systems, black is transmitted between
active video lines. With CRT displays, when the electron beam
has completed writing a horizontal line on the screen (at the
right side), the beam is deflected quickly to the left side of the
screen (called horizontal retrace) and a black signal is provided
to prevent the beam from disturbing the image.
In systems with embedded sync, a blacker-than-black signal
(Hsync) is produced briefly to signal the CRT that it is time to
begin a retrace. Because the input is not at black level at this
time, it is important to avoid clamping during Hsync.
Fortunately, there is virtually always a period following Hsync,
called the ‘back porch’, where a good black reference is provided.
This is the time when clamping should be done.
The clamp timing can be established by simply exercising the
CLAMP pin at the appropriate time with clamp source
(Register 0x18, Bit 4) = 1. The polarity of this signal is set by
the clamp polarity bit (Register 0x1B, Bits [7:6]).
A simpler method of clamp timing uses the AD9980’s internal
clamp timing generator. The clamp placement register
(Register 0x19) is programmed with the number of pixel
periods that should pass after the trailing edge of Hsync before
clamping starts. A second register, clamp duration, (Register
0x1A) sets the duration of the clamp. These are both 8-bit
values, providing considerable flexibility in clamp generation.
The clamp timing is referenced to the trailing edge of Hsync
because, though Hsync duration can vary widely, the back porch
(black reference) always follows Hsync. A good starting point
for establishing clamping is to set the clamp placement to 0x04
(providing 4 pixel periods for the graphics signal to stabilize
after sync) and set the clamp duration to 0x28 (giving the clamp
40 pixel periods to reestablish the black reference).
Clamping is accomplished by placing an appropriate charge on
the external input coupling capacitor. The value of this capacitor
affects the performance of the clamp. If it is too small, there will
be a significant amplitude change during a horizontal line time
(between clamping intervals). If the capacitor is too large, then
it will take excessively long for the clamp to recover from a large
change in incoming signal offset. The recommended value
(47 nF) results in recovering from a step error of 100 mV to
within ½ LSB in 20 lines with a clamp duration of 20 pixel
periods on a 85 Hz XGA signal.
YPbPr Clamping
YPbPr graphic signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) for the
color difference signals is at the midpoint of the video signal
rather than at the bottom. The three inputs are composed of
luminance (Y) and color difference (Pb and Pr) signals. For the
color difference signals it is necessary to clamp to the midscale
range of the ADC range (128) rather than at the bottom of the
ADC range (0) while the Y channel is clamped to ground.
Clamping to midscale rather than ground can be accomplished
by setting the clamp select bits in the serial bus register. Each of
the three converters has its own selection bit so that they can be
independently clamped to either midscale or ground. These bits
are located in Register 0x18, Bits [3:1]. The midscale reference
voltage is internally generated for each converter.
GAIN AND OFFSET CONTROL
The AD9980 contains three PGAs, one for each of the three
analog inputs. The range of the PGA is sufficient to accom-
modate input signals with inputs ranging from 0.5 V to 1.0 V
full scale. The gain is set in three 7-bit registers (red gain [0x05],
green gain [0x07], blue gain [0x09]). For each register, a gain
setting of 0 corresponds to the highest gain, while a gain setting
of 127 corresponds to the lowest gain. Note that increasing the
gain setting results in an image with less contrast.
The offset control shifts the analog input, resulting in a change
in brightness. Three 9-bit registers (red offset [0x0B, 0x0C],
green offset [0x0D, 0x0E], blue offset [0x0F, 0x10]) provide
independent settings for each channel. The function of the
offset register depends on whether auto-offset is enabled
(Register 0x1B, Bit 5).
If manual offset is used, seven bits of the offset registers (for the
red channel Register 0x0B, Bits [6:0] control the absolute offset
added to the channel. The offset control provides ±63 LSBs of
adjustment range, with one LSB of offset corresponding to one
LSB of output code.
Automatic Offset
In addition to the manual offset adjustment mode, the AD9980
also includes circuitry to automatically calibrate the offset for
each channel. By monitoring the output of each ADC during
the back porch of the input signals, the AD9980 can self-adjust
to eliminate any offset errors in its own ADC channels and any
offset errors present on the incoming graphics or video signals.
To activate the auto-offset mode, set Register 0x1B, Bit 5 to 1.
Next, the target code registers (0x0B through 0x10) must be
programmed. The values programmed into the target code
registers should be the output code desired from the AD9980
ADCs, which are generated during the back porch reference
time. For example, for RGB signals, all three registers are
normally programmed to Code 1, while for YPbPr signals the
green (Y) channel is normally programmed to Code 1 and the
blue and red channels (Pb and Pr) are normally set to 128. The
target code registers have nine bits per channel and are in twos
complement format. This allows any value between –256 and
+255 to be programmed. Although any value in this range can
be programmed, the AD9980’s offset range may not be able to
reach every value. Intended target code values range from (but
are not limited to) –40 to –1 and +1 to +40 when ground
clamping and +88 to +168 when midscale clamping. (Note that
a target code of 0 is not valid.)
Rev. 0 | Page 11 of 44
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