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PDF HT9172 Data sheet ( Hoja de datos )
| Número de pieza | HT9172 | |
| Descripción | DTMF Receiver | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HT9172 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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HT9172
DTMF Receiver
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Operating voltage: 2.5V~5.5V
· Minimal external component requirements
· No external filter required
· Low standby current in power down mode)
· Excellent performance
· Tristate data output for MCU interface
· 3.58MHz crystal or ceramic resonator oscillator
· 1633Hz can be inhibited by the INH pin
· 18-pin DIP/SOP packaging
General Description
The HT9172 is a Dual Tone Multi Frequency (DTMF) re-
ceiver device which includes an integrated digital de-
coder and band split filter functions as well as
power-down and inhibit mode operations. The device
uses digital counting techniques to detect and decode
the full range of 16 DTMF tone pairs into a 4-bit code
output. Highly accurate switched capacitor filters are uti-
lised to divide the DTMF dual tone frequencies into low
and high group signals. An integrated dial tone rejection
circuit is provided to eliminate the need for pre-filtering.
Block Diagram
X2
3 .5 8 M H z
X 1 C ry s ta l
O s c illa to r
PW DN
VREF
B ia s
C ir c u it
V re f
G e n e ra to r
R T /G T E S T D V D V B
S te e r in g C o n tr o l C ir c u it
VP
O PA
VN
GS
P r e - F ilte r
L o w G ro u p
F ilte r
H ig h G r o u p
F ilte r
F re q u e n c y
D e te c to r
C ode
D e te c to r
L a tc h
&
O u tp u t
B u ffe r
D0
D1
D2
D3
IN H O E
Rev. 1.00
DataSheet4 U .com
1 March 30, 2006
1 page  
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V DD
T one 100kW
0 .1 m F
100kW
3 .5 7 9 5 4 5 M H z
20pF 20pF
1 V P V D D 1 8 0 .1 m F
2 V N R T /G T 1 7
3 GS
E S T 16
4 VREF
D V 15 300kW
5 IN H
D 3 14
6 PW DN
D 2 13
7 X 1 D 1 12
8 X 2 D 0 11
9 VSS
O E 10
H T9172
Figure 1. Test Circuit
0 .1 m F
HT9172
Functional Description
Overview
The HT9172 tone decoder consists of three band pass
filters and two digital decode circuits to convert a DTMF
tone into a digital code output.
The device contains an operational amplifier to adjust
the input signal level as shown in Figure 2.
(a ) S ta n d a r d In p u t C ir c u it
C R1
Vi
VP
VN
H T9172
RF GS
VREF
(b ) D iffe r e n tia l In p u t C ir c u it
C1 R1
V i1
V i2
C2 R2
R3 R4
R5
VP
VN
H T9172
GS
VREF
Figure 2. Amplifier Input Application Circuits
The pre-filter is a band rejection filter which will reject
frequencies between 350Hz to 400Hz.
The low group filter, filters the low group frequency sig-
nal output whereas the high group filter, filters the high
group frequency signal output.
Each filter output is followed by a zero-crossing detector
with incorporates hysteresis. When the signal amplitude
at the output exceeds a specified level, it is transferred
to a full swing logic signal.
When the input signal is recognized as an effective
DTMF tone, the DV line will go high, and the corre-
sponding DTMF tone code will be generated.
Steering Control Circuit
The steering control circuit is used to measure the effec-
tive signal duration and for protecting against valid sig-
nal drop out. This is achieved using an analog delay
which is implemented using an external RC time-con-
stant, controlled by the output line EST.
The timing diagram is shown in Figure 3. The EST pin is
normally low and will pull the RT/GT pin low via the ex-
ternal RC network. When a valid tone input is detected,
the EST pin will go high, which will in turn pull the RT/GT
pin high through the RC network.
When the voltage on RT/GT rises from 0 to VTRT, which
is 2.35V for a 5V power supply, the input signal is effec-
tive, and the corresponding code will be generated by
the code detector. After D0~D3 have been latched, DV
will go high. When the voltage on RT/GT falls from VDD
to VTRT, i.e. when there is no input tone, the DV output
will go low, and D0~D3 will maintain their present data
until a next valid tone input is produced.
By selecting suitable external RC values, the minimum
acceptable input tone duration, tACC, and the minimum
acceptable inter-tone rejection, tIR, can be set. The values
of the external RC components, can be chosen using the
following formula. Also refer to Figure 5 for details.
tACC=tDP+tGTP;
tIR=tDA+tGTA;
where tACC: Tone duration acceptable time
tDP: EST output delay time (²L²®²H²)
tGTP: Tone present time
tIR: Inter-digit pause rejection time
Rev. 1.00
5 March 30, 2006
DataSheet4 U .com
5 Page 
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Product Tape and Reel Specifications
Reel Dimensions
T2
D
HT9172
AB
C
T1
SOP 18W
Symbol
A
B
C
D
T1
T2
Description
Reel Outer Diameter
Reel Inner Diameter
Spindle Hole Diameter
Key Slit Width
Space Between Flange
Reel Thickness
Dimensions in mm
330±1.0
62±1.5
13.0+0.5
-0.2
2.0±0.5
24.8+0.3
-0.2
30.2±0.2
Rev. 1.00
DataSheet4 U .com
11 March 30, 2006
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet HT9172.PDF ] | |
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