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PDF AX88655AB Data sheet ( Hoja de datos )
| Número de pieza | AX88655AB | |
| Descripción | 5-Port 10/100/1000BASE-T Ethernet Switch | |
| Fabricantes | ASIX Electronics | |
| Logotipo |  |
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AX88655 AB
5-Port 10/100/1000BASE-T Ethernet Switch
5-Port Gigabit Ethernet Switch with Embedded Memory
Document No.: AX88655AB / V0.8 / June 11, 2003
Features
• 5-port Gigabit Ethernet switch integrating MACs,
packet buffer memory and switching engine with
• Programmable aging mechanism for the two-way
4K MAC addresses table
RGMII/GMII/MII interface
• RGMII support REV 1.3 with 3.3V IO
• Full Duplex 1000 Mbit/s.
• Full and Half Duplex 10/100 Mbit/s
• Supports auto-sensing or manual selection for
• Two hashing schemes: direct and XOR mode.
• Support ingress port security mode, incoming
packets with unknown source MAC address could
be dropped
• Egress/Ingress Port Mirroring for Sniffer function.
speed and duplex capability with an embedded
MPU
• Store-and-forward operation support
• Performs full wire-speed switching with Head of
Line (HOL) blocking prevention
• Flow control
- Full-duplex IEEE 802.3x flow control
- Half-duplex back pressure flow control
- Optional smart flow control for mix-speed
connection
• Supports up to 8 Port-based VLAN Groups
• Supports broadcast storm filtering.
• Quality-of-Service provisioning on 802.1P tag and
port-pairs with two priority queues
• By-port Egress/Ingress bandwidth (rate) control
• Embedded 128K Byte SRAM for packet buffer
• Supports packet length up to 1522 bytes
• Supports 9K/12K byte JUBMO packet
• Integrated two-way Address-Lookup engine and
• Supports port-based trunking for high-bandwidth
links
• Provides 5 GPIO ports
• Provides EEPROM interface for auto-configuration
• System clock input is one 25MHz Crystal and one
125MHz from PHY GCLK output
• 1.8 and 3.3V operations
• 3.3 I/Os and packaged in 272-pin BGA
table for 4K MAC addresses
Product Description
The AX88655AB is an 5-port 10/100/1000 Mbps Ethernet switch with, GMII/RGMII or MII Interface. The switch
controller provides network system manufacturers the ideal platform for building smart and cost-effective backbone
switches for small to medium sized businesses.
The AX88655AB 5-port 10/100/100 BASE-T single chip switch controllers combine the benefits of network
simplicity, flexibility and high integration. Its highly integrated feature set enables network system manufacturers to
build smart switches for the fast-growing small to medium business market segment.
Benefits of AX88655AB Switches are below.
Simplicity
Provides a smart, simple and low maintenance plug-and-play network interconnect system for small to
medium size businesses
Flexibility
Highly scalable configuration allows system manufacturers to enable or disable a range of features to best
meet their target price point.
Integration
Highly integrated design drives down overall switch manufacturing costs.
Target Applications
5-port Gigabit Layer 2 Switches for workgroup
High-port count Layer 2 switches with trunking
High performance solution of Ethernet backbone
ASIX ELECTRONICS CORPORATION
First Released Date: 11/07/2002
4F, NO.8, Hsin Ann Rd., Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-563-9799
http://www.asix.com.tw
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AX88655AB 5-Port 10/100/1000BASE-T Ethernet Switch CONFIDENTIAL
1.0 AX88655AB Overview
1.1 General Description
The AX88655AB Gigabit switch controller supports eight 10/100/1000 Mbps ports in wire-speed operation. The
AX88655AB Gigabit switch controller provides eight 10/100/1000 Ethernet ports with RGMII/GMII/MII interface. For
each ports, the AX88655AB supports GMII/RGMII (802.3ab, 1000BASE-T) interface with full-duplex operation at
Gigabit speed, full- or half-duplex operation at 10/100 Mbps speed (using 802.3/u, 10/100BASE-T) and polls the status
of PHYs with an embedded MPU.
The device supports 4K internal MAC addresses which are shared by all ports with an embedded SRAM. The
learning/routing engine is implemented with a two-way hash/linear algorithm to reduce possibility of routing collision.
Basically the AX88655AB supports non-blocking wire speed forwarding rate and no Head-of-Line (HOL) blocking
issue. The AX88655AB provides two flow-control mechanisms to avoid loss of data: an optional jamming based
backpressure flow control in the half-duplex operation and IEEE 802.3x in the full-duplex mode.
To support Quality of Service (QoS), each output port has two priority queues and their assignment can be based on the
802.1p priority field or Port-Pair setting. Each output port retrieves the frames from the shared buffer based on queuing
and sends them to the transmitting (Tx) FIFO.
1.2 AX88655AB Block Diagram
RGMII/GMII PHY
RGMII/GMII PHY
RGMII/GMII PHY
RGMII/GMII PHY
RGMII/GMII PHY
10/100/1000 MAC
10/100/1000 MAC
10/100/1000 MAC
10/100/1000 MAC
10/100/1000 MAC
GPIO
General Purpose
I/O Interface (GPIO)
High Speed
Switch Fabric
Configuration
Logic
Routing /Learning
Engine
Address Look-up Table
Buffer Manager
Packet
Buffer
EEPROM
Interface
Fig-1 AX88655AB Block Diagram
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AX88655AB 5-Port 10/100/1000BASE-T Ethernet Switch CONFIDENTIAL
3.0 Functional Description
3.1 Introduction
In general, the AX88655AB device is a highly integrated Layer 2 switch. It supports eight 10/100/1000 ports with
on-chip MACs. It also supports integrated switching logic, packet queuing memory and packet storage memory. The
AX88655AB is capable of routing-and-forwarding packets at wire speed on all ports regardless of packet size.
It is a low cost solution for eight ports Gigabit Ethernet backbone switch design. No CPU interface is required; After
power on reset, AX88655AB provide an auto load configuration setting function through a 2 wire serial EEPROM
interface to access external EEPROM device, and AX88655AB can easily be configured to support trunking, QoS, IEEE
802.3x flow control threshold setting, broadcast storm control ...etc functions. An overview of AX88655AB’s major
functional blocks is shown in Fig-1.
3.2 Packet Filtering and Forwarding Process
The switch use simple store-and-forward algorithm as packet switching method. After receives incoming packets, the
packets will be stored to the embedded memory first. The AX88655AB searches in the Address-Lookup Table with DA
of the packet. The packet will be forward to its destination port, if this packet’s DA hits; otherwise this packet will be
broadcasted. Of course, only good packets will be forward.
3.3 MAC Address Routing, Learning and Aging Process
The switch supports 4K MAC entries for switching. Two-way dynamic address learning is performed by each good
unicast packet is completely received. And linear/XOR hash algorithm of the static address learning is achieved by
EEPROM configuration. On the other hand, the routing process is performed whenever the packet’s DA is captured. If
the DA can not get a hit result, the packet is going to broadcast.
Only the learned address entries are scheduled in the aging machine. If one station does not transmit any packet for a
period of time, the belonging MAC address will be kicked out from the address table. The aging out time can be program
automatically through the EEPROM configuration. (Default value is 300 seconds)
3.4 Full Duplex 802.3x Flow Control
In full duplex mode, AX88655AB supports the standard flow control mechanism defined in IEEE 802.3x standard. It
enables the stopping of remote node transmissions via a PAUSE frame information interaction. When space of the packet
buffer is less than the initialization setting threshold value, AX88655AB will send out a PAUSE-ON packet with pause
time equal to “xFFF” to stop the remote node transmission. And then AX88655AB will send out a PAUSE-OFF packet
with pause time equal to zero to inform the remote node to retransmit packet if has enough space to receive packets.
3.5 Half Duplex Back Pressure Control
In half duplex mode, AX88655AB provide a backpressure control mechanism to avoid dropping packets during network
conjection situation. When space of the packet buffer is less than the initialization setting threshold value, AX88655AB
will send a JAM pattern in the input port when it senses an incoming packet, thus force a collision to make the remote
node transmission back off and will effectively avoid dropping packets. And then AX88655AB will not send out a JAM
packet any more if has enough space to receive one packet.
3.6 MII Polling
The AX88655AB supports PHY management through the serial MDIO/MDC interface. That is, the AX88655AB access
related register of PHYs via MDIO/MDC interface after power on reset. The AX88655AB will periodically and
continuously poll and update the link status and link partner’s ability which include speed, duplex mode, and 802.3x flow
control capable status of the connected PHY devices through MDIO/MDC serial interface.
3.7 Port-Based QoS: Port-Pair
11
ASIX ELECTRONICS CORPORATION
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