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PDF MB91350A Data sheet ( Hoja de datos )
| Número de pieza | MB91350A | |
| Descripción | (MB9135xA) 32-Bit Proprietary Microcontroller | |
| Fabricantes | Fujitsu Media Devices | |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16504-3E
32-Bit Proprietary Microcontroller
CMOS
FR60 MB91350A Series
MB91F355A/F356B/355A/354A/V350A
■ DESCRIPTION
The FR families are lines of standard single-chip microcontrollers each based on a 32-bit high-performance RISC
CPU, incorporating a variety of I/O resources and bus control features for embedded control applications which
require high CPU performance for
This FR60 family is based on FR30 and FR40 families and enhanced is bus access. The FR60 family is a line of
single-chip oriented microcontrollers incorporating a wealth of peripheral resources.
The FR60 family is optimized for embedded control applications requiring high processing power of the CPU,
such as DVD player, navigation, high performance Fax machine, and printer controls.
■ FEATURES
1. FR CPU
• 32-bit RISC, load/store architecture with a five-stage pipeline
• Maximum operating frequency: 50 MHz (using the PLL at an oscillation frequency of 12.5 MHz)
• 16-bit fixed length instructions (basic instructions), 1 instruction per cycle
• Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift
etc.
• Instructions adapted for high-level languages: Function entry/exit instructions, multiple-register load/store in-
structions
■ PACKAGE
(Continued)
176-pin plastic LQFP
(FPT-176P-M02)
I2C license
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system
provided that the system conforms to the I2C Standard Specification as defined by Philips.
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MB91350A Series
■ PIN DESCRIPTION
Pin no.
Pin name
Circuit
type
Description
D16 to D23
External data bus bit 16 to bit 23. Enabled in external bus mode.
1 to 8
C
P20 to P27
Available as a port in external bus 8-bit mode.
D24 to D31
external data bus bit 24 to bit 31. Enabled in external bus mode.
9 to 16
C
P30 to P37
Usable as port at single chip mode.
A00 to A07
19 to 26
P40 to P47
Bits 0 to 7 of external address bus. Enabled in external bus mode.
C
Usable as port at single chip mode.
A08 to A15
27 to 34
P50 to P57
Bits 8 to 15 of external address bus. Enabled in external bus mode.
C
Usable as port at single chip mode.
A16 to A20
37 to 41
P60 to P64
Bits 16 to 20 of external address bus. Enabled in external bus mode.
C Available as a port either in single chip mode or with no external address bus in
use.
A21 to A23
42 to 44
P65 to P67
Bits 21 to 23 of external address bus. Enabled in external bus mode.
C Available as a port either in single chip mode or with no external address bus in
use.
47 to 48 DA0, DA1 ⎯ D/A converter output pin.
49 DA2 ⎯ D/A converter output pin.
50 to 57 AN0 to AN7 G Analog input pin.
58 to 61 AN8 to AN11 G Analog input pin.
TOT0 to TOT3
Reload timer output port. This function is enabled when timer output is enabled.
67 to 70
PP0 to PP3
D
General purpose input/output port. This function is enabled when the timer out-
put function is disabled.
OC0
Output compare pin.
71
PO0
D General purpose I/O. This function is available as a port when the output com-
pare output is not in use.
OC1
Output compare pin.
72
PO1
D General purpose I/O. This function is available as a port when the output com-
pare output is not in use.
OC2
Output compare pin.
73
PO2
D General purpose I/O. This function is available as a port when the output com-
pare output is not in use.
OC3 to OC7
Output compare pin.
74 to 78
PO3 to PO7
D
General purpose I/O. This function is available as a port when the output com-
pare output is not in use.
PPG0
PPG timer output pin.
81
PN0
D General purpose I/O. This function is available as a port when the PPG timer out-
put is not in use.
(Continued)
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MB91350A Series
Pin no.
152
153
154
155
156
157
158
159
160
Pin name
Circuit
type
Description
DEOP0
Completion output for DMA external transfer. This function is enabled when the
external transfer end output for DMA is enabled.
DSTP0
C
Stop input for DMA external transfer. This function is enabled when the external
transfer stop input for DMA is enabled.
PB2
General purpose input/output port. This function is enabled when the external
transfer end output and external transfer stop input for DMA are disabled.
DREQ1
External input for DMA transfer requests. Since this input is used as required
when selected as a DMA start source, the port output must remain off unless in-
C tentionally turned on.
PB3 General purpose input/output port.
DACK1
PB4
External acknowledge output for DMA transfer requests. This function is enabled
when the transfer request acceptance output for DMA is enabled.
C
General purpose input/output port. This function is enabled when the external
transfer request acceptance output for DMA is disabled.
DEOP1
Completion output for DMA external transfer. This function is enabled when the
external transfer end output for DMA is enabled.
DSTP1
C
Stop input for DMA external transfer. This function is enabled when the external
transfer stop input for DMA is enabled.
PB5
General purpose input/output port. This function is enabled when the external
transfer end output and external transfer stop input for DMA are disabled.
IOWR
PB6
Write strobe output for DMA fly-by transfer. This function is enabled when the
DMA fly-by transfer write strobe output is enabled.
C
General purpose input/output port. This function is enabled when the DMA fly-by
transfer write strobe output is disabled.
IORD
PB7
Read storobe output for DMA fly-by transfer. This function is enabled when the
DMA fly-by transfer read strobe output is enabled.
C
General purpose input/output port. This function is enabled when the DMA fly-by
transfer read strobe output is disabled.
CS0 Chip select 0 output. Enable at external bus mode
C
PA0 General purpose input/output port. This is enabled at single chip mode.
CS1
Chip select 1 output. This function is enabled when the chip select 1 output is en-
abled.
C
PA1
General purpose input/output port. This function is enabled when the chip select
1 output is disabled.
CS2
Chip select 2 output. This function is enabled when the chip select 2 output is en-
abled.
C
PA2
General purpose input/output port. This function is enabled when the chip select
2 output is disabled.
(Continued)
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