PDF CY2318BNZ Data sheet ( Hoja de datos )

Número de pieza	CY2318BNZ
Descripción	3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com CY2318BNZ 18 Output, 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs Features Functional Description • One input to 18 output buffer/driver • Supports up to four SDRAM DIMMs • Two additional outputs for feedback • SMBus interface for individual output control • Low skew outputs (< 200 ps) • Up to 100 MHz operation for Industrial temperatures • Up to 133 MHz operation for Commercial temperatures • Dedicated OE pin for testing • Space-saving 48-pin SSOP package • 3.3V operation The CY2318BNZ is a 3.3V buffer designed to distribute high-speed clocks in PC applications. The part has 18 outputs, 16 of which can be used to drive up to four SDRAM DIMMs, and the remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 100 MHz, thus making it compatible with Pentium II® processors. The CY2318BNZ can be used in conjunction with the CY2280, CY2281, CY2282 or similar clock synthesizer for a complete Pentium II motherboard solution. The CY2318BNZ also includes an SMBus interface which can enable or disable each output clock. On power-up, all output clocks are enabled (internal pull up). A separate Output Enable pin facilitates testing on ATE. Block Diagram BUF_IN SDATA SCLOCK SMBus Decoding OE Pentium II is a registered trademark of Intel Corporation. SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 SDRAM13 SDRAM14 SDRAM15 SDRAM16 SDRAM17 Pin Configuration NC NC VDD SDRAM0 SDRAM1 VSS VDD SDRAM2 SDRAM3 VSS BUF_IN VDD SDRAM4 SDRAM5 VSS VDD SDRAM6 SDRAM7 VSS VDD SDRAM16 VSS VDDIIC SDATA SSOP Top View 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 NC NC VDD SDRAM15 SDRAM14 VSS VDD SDRAM13 SDRAM12 VSS OE VDD SDRAM11 SDRAM10 VSS VDD SDRAM9 SDRAM8 VSS VDD SDRAM17 VSS VSSIIC SCLOCK Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-07217 Rev. Revised December 4, 2001 DataSheet4 U .com 1 page www.DataSheet4U.com CY2318BNZ AC Electrical Characteristics: TA = –40°C to +85°C, VDDQ3 = 3.3V±5% (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition fIN Input Frequency Commercial Temperature Range tR Output Rise Edge Rate Measured from 0.4V to 2.4V tF Output Fall Edge Rate Measured from 2.4V to 0.4V tSR Output Skew, Rising Edges tSF Output Skew, Falling Edges tEN Output Enable Time tDIS Output Disable Time tPR Rising Edge Propagation Delay tPF Falling Edge Propagation Delay tD Duty Cycle Measured at 1.5V Zo AC Output Impedance Notes: 2. OE, SCLOCK, and SDATA logic pins have a 250-kΩ internal pull-up resistor (not CMOS level). 3. Outputs loaded by 6" 60Ω transmission lines with 20-pF capacitors. Min 0 1.5 1.5 1.0 1.0 3.0 3.0 50 Typ 3.85 3.85 15 Max Unit 133 MHz 4.0 V/ns 4.0 V/ns 200 ps 200 ps 8.0 ns 8.0 ns 5.0 ns 5.0 ns 60 % Ω Test Circuit 0.1 µF VDD OUTPUTS GND CLK out CLOAD Document #: 38-07217 Rev. DataSheet4 U .com Page 5 of 8 5 Page

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