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PDF CY2318ANZ Data sheet ( Hoja de datos )
| Número de pieza | CY2318ANZ | |
| Descripción | 3.3V SDRAM Buffer for Desktop PCs with 4 DIMMs | |
| Fabricantes | Cypress Semiconductor | |
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Features
• One input to 18 output buffer/driver
• Supports up to four SDRAM DIMMs
• Two additional outputs for feedback
• Serial interface for individual output control
• 150ps typical output-output skew
• Up to 100 MHz operation
• Dedicated OE pin for testing
• Space-saving 48-pin SSOP package
• 3.3V operation
CY2318ANZ
18 Output, 3.3V SDRAM Buffer for
Desktop PCs with 4 DIMMs
Functional Description
The CY2318ANZ is a 3.3V buffer designed to distribute
high-speed clocks in PC applications. The part has 18 outputs,
16 of which can be used to drive up to four SDRAM DIMMs,
and the remaining can be used for external feedback to a PLL.
The device operates at 3.3V and outputs can run up to 100
MHz, thus making it compatible with Pentium II® processors.
The CY2318ANZ can be used in conjunction with the CY2280,
CY2281, CY2282 or similar clock synthesizer for a complete
Pentium II motherboard solution.
The CY2318ANZ also includes a serial interface which can
enable or disable each output clock. On power-up, all output
clocks are enabled (internal pull up). A separate Output
Enable pin facilitates testing on ATE.
Block Diagram
BUF_IN
SDATA
SCLOCK
Serial Interface
Decoding
OE
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
SDRAM13
SDRAM14
SDRAM15
SDRAM16
SDRAM17
Pin Configuration
NC
NC
VDD
SDRAM0
SDRAM1
VSS
VDD
SDRAM2
SDRAM3
VSS
BUF_IN
VDD
SDRAM4
SDRAM5
VSS
VDD
SDRAM6
SDRAM7
VSS
VDD
SDRAM16
VSS
VDDIIC
SDATA
SSOP
Top View
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
NC
NC
VDD
SDRAM15
SDRAM14
VSS
VDD
SDRAM13
SDRAM12
VSS
OE
VDD
SDRAM11
SDRAM10
VSS
VDD
SDRAM9
SDRAM8
VSS
VDD
SDRAM17
VSS
VSSIIC
SCLOCK
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07181 Rev. *B
Revised January 19, 2005
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Switching Characteristics[4]
Parameter
Name
Maximum Operating Frequency
Duty Cycle[3, 5] = t2 ÷ t1
t3 Rising Edge Rate[3]
t4 Falling Edge Rate[3]
t5 Output to Output Skew[3]
t6 SDRAM Buffer LH Prop. Delay[3]
t7 SDRAM Buffer HL Prop. Delay[3]
t8 SDRAM Buffer Enable Delay[3]
t9 SDRAM Buffer Disable Delay[3]
Test Conditions
Measured at 1.5V
Measured between 0.4V and 2.4V
Measured between 2.4V and 0.4V
All outputs equally loaded
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
Input edge greater than 1 V/ns
CY2318ANZ
Min. Typ. Max. Unit
100 MHz
45.0 50.0 55.0
%
0.9 1.5 4.0 V/ns
0.9 1.5 4.0 V/ns
150 250
ps
1.0 3.5 5.0 ns
1.0 3.5 5.0 ns
1.0 5
12 ns
1.0 20 30 ns
Switching Waveforms
Duty Cycle Timing
1.5V
t1
t2
1.5V
1.5V
All Outputs Rise/Fall Time
2.4V
OUTPUT 0.4V
t3
Output-Output Skew
2.4V
0.4V
t4
3.3V
0V
OUTPUT
1.5V
OUTPUT
t5
1.5V
Notes:
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns.
Document #: 38-07181 Rev. *B
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CY2318ANZ.PDF ] | |
Hoja de datos destacado
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