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PDF CY2313ANZ Data sheet ( Hoja de datos )

Número de pieza CY2313ANZ
Descripción 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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0NZCY 2310
13ANZ
Features
• One input to 13 output buffer/driver
• Supports up to three SDRAM DIMMs
• One additional outputs for feedback
• Serial interface for output control
• Low skew outputs
• Up to 100-MHz operation
• Multiple VDD and VSS pins for noise reduction
• Low EMI outputs
• 28-pin SOIC (300-mil) package
• 3.3V operation
Block Diagram
CY2313ANZ
13 Output, 3.3V SDRAM Buffer for
Desktop PCs with 3 DIMMs
Functional Description
The CY2313ANZ is a 3.3V buffer designed to distribute
high-speed clocks in desktop PC applications. The part has 13
outputs, 12 of which can be used to drive up to three SDRAM
DIMMs, and the remaining can be used for external feedback
to a PLL. The device operates at 3.3V and outputs can run up
to 100 MHz, thus making it compatible with Pentium® II pro-
cessors. The CY2313ANZ can be used in conjunction with the
CY2280, CY2281, CY2282 or similar clock synthesizer for a
complete Pentium II motherboard solution.
The CY2313ANZ also includes a serial interface which can
enable or disable each output clock. On power-up, all output
clocks are enabled.
Pin Configuration
BUF_IN
SDATA
SCLOCK
Serial Interface
Decoding
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
VDD
SDRAM0
SDRAM1
VSS
VDD
SDRAM2
SDRAM3
VSS
BUF_IN
SDRAM4
SDRAM5
SDRAM12
VDDIIC
SDATA
28 SOIC
Top View
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VDD
SDRAM11
SDRAM10
VSS
VDD
SDRAM9
SDRAM8
VSS
VDD
SDRAM7
SDRAM6
VSS
VSSIIC
SCLK
Pentium is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07144 Rev. *A
Revised December 14, 2002
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CY2313ANZ pdf
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Switching Waveforms (continued)
SDRAM Buffer LH and HL Propagation Delay
INPUT
OUTPUT
t6
SDRAM Buffer Enable and Disable Times
t7
OE
Three-State
OUTPUTS
t8
Active
t9
Test Circuit
0.1 µF
VDD
OUTPUTS
GND
CY2313ANZ
CLK out
CLOAD
Document #: 38-07144 Rev. *A
DataSheet4 U .com
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