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Número de pieza | CY7C1007 | |
Descripción | (CY7C107 / CY7C1007) 1M x 1 Static RAM | |
Fabricantes | Cypress Semiconductor | |
Logotipo | ||
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CY7C107
CY7C1007
Features
• High speed
— tAA = 12 ns
• CMOS for optimum speed/power
• Low active power
— 825 mW
• Low standby power
— 275 mW
• 2.0V data retention (optional)
— 100 µW
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Functional Description
The CY7C107 and CY7C1007 are high-performance CMOS
static RAMs organized as 1,048,576 words by 1 bit. Easy
1M x 1 Static RAM
memory expansion is provided by an active LOW Chip Enable
(CE) and three-state drivers. These devices have an automatic
power-down feature that reduces power consumption by more
than 65% when deselected.
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the input pin
(DIN) is written into the memory location specified on the ad-
dress pins (A0 through A19).
Reading from the devices is accomplished by taking Chip En-
able (CE) LOW while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the data output (DOUT)
pin.
The output pin (DOUT) is placed in a high-impedance state
when the device is deselected (CE HIGH) or during a write
operation (CE and WE LOW).
The CY7C107 is available in a standard 400-mil-wide SOJ; the
CY7C1007 is available in a standard 300-mil-wide SOJ.
Logic Block Diagram
INPUT BUFFER
A0
A1
A2
A3
A4 512x2048
A5 ARRAY
A6
A7
A8
COLUMN
DECODER
POWER
DOWN
DIN
DOUT
CE
WE
107-1
Pin Configuration
SOJ
Top View
A10
A11
A12
A13
A14
A15
NC
A16
A17
A18
A19
DOUT
WE
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 A9
26 A8
25
24
A7
A6
23 A5
22
21
A4
NC
20 A3
19
18
17
A2
AA01
16 DIN
15 CE
107-2
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum Standby
Current (mA)
7C107-12
7C1007-12
12
150
50
7C107-15
7C1007-15
15
135
40
7C107-20
7C1007-20
20
125
30
7C107-25
7C1007-25
25
120
30
7C107-35
35
110
25
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 1992 – Revised September 3, 1999
DataSheet4 U .com
1 page www.DataSheet4U.com
CY7C107
CY7C1007
Data Retention Characteristics Over the Operating Range (L Version Only)
Parameter
Description
Conditions[9]
VDR
ICCDR
tCDR[4]
tR[4]
VCC for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3 or
VIN < 0.3V
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
VDR > 2V
tCDR
CE
Min.
2.0
0
tRC
Max.
50
Unit
V
µA
ns
ns
4.5V
tR
107-5
Switching Waveforms
Read Cycle No. 1[10, 11]
ADDRESS
DATA OUT
tOHA
PREVIOUS DATA VALID
tAA
Read Cycle No. 2[11, 12]
tRC
DATA VALID
107-6
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT
tACE
tLZCE
HIGH IMPEDANCE
tPU
50%
Notes:
9. No input may exceed VCC + 0.5V.
10. Device is continuously selected, CE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
tRC
DATA VALID
tHZCE
HIGH
IMPEDANCE
tPD
50%
ICC
ISB
107-7
DataSheet4 U .com
5
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet CY7C1007.PDF ] |
Número de pieza | Descripción | Fabricantes |
CY7C1006B | 256K x 4 Static RAM | Cypress Semiconductor |
CY7C1007 | (CY7C107 / CY7C1007) 1M x 1 Static RAM | Cypress Semiconductor |
CY7C1007D | 1-Mbit (1 M x 1) Static RAM | Cypress Semiconductor |
CY7C1009 | 128K x 8 Static RAM | Cypress Semiconductor |
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