PDF CY7C1355C Data sheet ( Hoja de datos )

Número de pieza	CY7C1355C
Descripción	(CY7C1355C / CY7C1357C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com PRELIMINARY CY7C1355C CY7C1357C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description[1] • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles. • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 3.3V/2.5V I/O power supply • Fast clock-to-output times — 6.5 ns (for 133-MHz device) — 7.0 ns (for 117-MHz device) — 7.5 ns (for 100-MHz device) • Clock Enable (CEN) pin to enable clock and suspend operation • Synchronous self-timed writes • Asynchronous Output Enable • Offered in JEDEC-standard 100 TQFP, 119-Ball BGA and 165-Ball fBGA packages • Three chip enables for simple depth expansion. • Automatic Power-down feature available using ZZ mode or CE deselect • JTAG boundary scan for BGA and fBGA packages • Burst Capability—linear or interleaved burst order • Low standby power The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by the two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. Selection Guide 133 MHz 117 MHz 100 MHz Maximum Access Time 6.5 7.0 7.5 Maximum Operating Current 250 220 180 Maximum CMOS Standby Current 30 30 30 Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Unit ns mA mA Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-05539 Rev. Revised April 12, 2004 DataSheet4 U .com 1 page www.DataSheet4U.com PRELIMINARY CY7C1355C CY7C1357C Pin Configurations (continued) 119-ball BGA (3 Chip Enables with JTAG) CY7C1355C (256K x 36) 1 234567 A VDDQ A A NC / 18M A A VDDQ B NC CE2 C NC A A ADV/LD A A VDD A CE3 NC A NC D DQC DQPC VSS E DQC DQC VSS F VDDQ DQC VSS NC CE1 OE VSS DQPB DQB VSS DQB DQB VSS DQB VDDQ G DQC DQC H DQC DQC J VDDQ VDD K DQD DQD BWC VSS NC VSS A WE VDD CLK BWB VSS NC VSS DQB DQB VDD DQA DQB DQB VDDQ DQA L DQD DQD BWD NC BWA DQA DQA M VDDQ DQD VSS CEN VSS DQA VDDQ N DQD DQD VSS A1 VSS DQA DQA P DQD DQPD VSS A0 R NC A MODE VDD VSS DQPA DQA NC A NC T NC NC / 72M A A A NC / 36M ZZ U VDDQ TMS TDI TCK TDO NC VDDQ CY7C1357C (512K x 18) 123 45 A VDDQ A A NC / 18M A B NC CE2 A ADV/LD A C NC A A VDD A D DQB NC VSS NC VSS E NC DQB VSS F VDDQ NC VSS CE1 OE VSS VSS G NC DQB BWB A VSS H DQB NC VSS WE VSS J VDDQ VDD NC VDD NC K NC DQB VSS CLK VSS L DQB NC VSS NC BWA M VDDQ DQB VSS CEN VSS N DQB NC VSS A1 VSS P NC DQPB VSS A0 VSS R NC A T NC / 72M A U VDDQ TMS MODE A TDI VDD NC / 36M TCK NC A TDO 6 A CE3 A DQPA NC DQA NC DQA VDD NC DQA NC DQA NC A A NC 7 VDDQ NC NC NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ NC DQA NC ZZ VDDQ Document #: 38-05539 Rev. DataSheet4 U .com Page 5 of 33 5 Page www.DataSheet4U.com PRELIMINARY CY7C1355C CY7C1357C Truth Table[2, 3, 4, 5, 6, 7, 8] Operation Deselect Cycle Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK DQ None H X X L L X X X L L->H Three-State Deselect Cycle None X X H L L X X X L L->H Three-State Deselect Cycle None X L X L L X X X L L->H Three-State Continue Deselect Cycle None X X X L H X X X L L->H Three-State READ Cycle (Begin Burst) External L H L L L H X L L L->H Data Out (Q) READ Cycle (Continue Burst) Next X X X L H X X L L L->H Data Out (Q) NOP/DUMMY READ (Begin Burst) External L H L L L H X H L L->H Three-State DUMMY READ (Continue Burst) Next X X X L H X X H L L->H Three-State WRITE Cycle (Begin Burst) External L H L L L L L X L L->H Data In (D) WRITE Cycle (Continue Burst) Next X X X L H X L X L L->H Data In (D) NOP/WRITE ABORT (Begin Burst) None L H L L L L HX L L->H Three-State WRITE ABORT (Continue Burst) Next X X X L H X H X L L->H Three-State IGNORE CLOCK EDGE (Stall) Current X X X L X X X X H L->H - SLEEP MODE None X X X H X X X X X X Three-State Notes: 2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write Selects are asserted, see Truth Table for details. 3. Write is defined by BWX, and WE. See Truth Table for Read/Write. 4. When a Write cycle is detected, all I/Os are three-stated, even during Byte Writes. 5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. CEN = H, inserts wait states. 7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE. 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQs OE is inactive or when the device is deselected, and DQs and DQPX = data when OE is active. and DQPX = Three-state when 9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active. Document #: 38-05539 Rev. ** DataSheet4 U .com Page 11 of 33 11 Page

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