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PDF AX88850 Data sheet ( Hoja de datos )
| Número de pieza | AX88850 | |
| Descripción | 100BASE-TX/FX Repeater Controller | |
| Fabricantes | ASIX Electronics Corporation | |
| Logotipo |  |
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ASIX
AX88850
100BASE-TX/FX Repeater Controller
ASIX AX88850
100BASE-TX/FX
Repeater Controller
Data Sheet(11/03/’97)
DOCUMENT NO. : AX850D2.DOC
This data sheets contain new products information. ASIX ELECTRONICS reserves the rights to modify the products
specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
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AX88850
PRELIMINARY
1.0 AX88850 Overview
The AX88850 series 100Mbps Repeater Controllers are designed for both low cost
dumb HUB and high performance intelligent HUB applications. The AX88850 series
product support up-to ten 100Mbps links with its 8 PCS (Physical coding sub-layer , also
called Symbol Interface) interfaces and 2 dedicated MII interfaces or supports up-to eighteen
100Mbps links with 2 shared 8 ports MII interfaces and 2 dedicated MII interfaces.
Maximum up-to 144 ports can be constructed when using expansion bus cascades 8
AX88850s. The AX88850 is designed base on IEEE 802.3u clause 27 “ Repeater for
100Mb/s base-band networks” . It is fully compatible with IEEE 802.3u standard.
1.1 General Description
The AX88850 Repeater Controller is a subset of a repeater set containing all the
repeater-specific components and functions, exclusive of PHY components and functions.
The AX88850 family has two kind of interfaces to connect to PHY devices. There are
Physical coding sub-layer (PCS) interface and Media Independent Interface (MII).
The AX88850 supports 8 PCS ports interface or 2 shared bus (8 ports/per bus) MII
interfaces, 2 dedicated MII ports interface, an expansion port interface, a management
information base IC interface, a repeater ID daisy chain interface, a serial register interface
and LED display interface.
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AX88850
PRELIMINARY
1.7 Pin Connection Diagram for AX88854 (Management mode)
IRD_CK
/IRD_V
/IRD_ER
VSS
IRD<0>
IRD<1>
IRD<2>
IRD<3>
/RST
TEST
VSS
LCLK
NC
NC
VDD
GEP<0>
GEP<1>
GEP<2>
GEP<3>
VSS
RDATA<0><0>
RDATA<0><1>
RDATA<0><2>
RDATA<0><3>
RDATA<0><4>
RSCLK<0>
RSD<0>
VDD1
VSS1
TDATA<0><0>
TDATA<0><1>
TDATA<0><2>
TDATA<0><3>
TDATA<0><4>
RDATA<1><0>
RDATA<1><1>
RDATA<1><2>
RDATA<1><3>
RDATA<1><4>
RSCLK<1>
RSD<1>
VSS
TDATA<1><0>
TDATA<1><1>
TDATA<1><2>
TDATA<1><3>
TDATA<1><4>
RDATA<2><0>
RDATA<2><1>
RDATA<2><2>
RDATA<2><3>
RDATA<2><4>
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186 M0_TXEN0
187 M0_TXEN1
188 M0_TXEN2
189 M0_TXEN3
190 M0_RXEN0
191 M0_CRS0
192 M0_CRS1
193 M0_CRS2
194 M0_CRS3
195
196
197
198
199 M0_RXEN1
200 M0_RXEN2
201 M0_RXEN3
202 M0_TXEN4
203 M0_TXEN5
204 M0_CRS4
205 M0_CRS5
206 M0_CRS6
207 M0_CRS7
208
ASIX
AX 88854
(Management Mode)
104
103
102
101
100
99
98
97
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
M1_RXEN7 78
M1_RXEN6 77
M1_RXEN5 76
M1_RXEN4 75
M1_TXEN7 74
73
72
71
70
69
68
67
66
M1_TXEN6 65
M1_TXEN5 64
M1_TXEN4 63
M1_RXEN3 62
M1_RXEN2 61
60
M1_RXEN1 59
58
57
M1_CRS7 56
M1_CRS6 55
M1_CRS5 54
M1_CRS4 53
RX_ER<1>
VDD
RXD<1><3>
RXD<1><2>
RXD<1><1>
RXD<1><0>
TX_EN<1>
TXD<3>
TXD<2>
TXD<1>
TXD<0>
VSS
TX_ER
COL
CRS<0>
RX_DV<0>
RX_CLK<0>
RX_ER<0>
RXD<0><3>
RXD<0><2>
RXD<0><1>
RXD<0><0>
TX_EN<0>
OPT0
VDD1
VSS1
TDATA<7><4>
TDATA<7><3>
TDATA<7><2>
TDATA<7><1>
TDATA<7><0>
VDD
RSD<7>
RSCLK<7>
RDATA<7><4>
RDATA<7><3>
RDATA<7><2>
RDATA<7><1>
RDATA<7><0>
TDATA<6><4>
TDATA<6><3>
TDATA<6><2>
TDATA<6><1>
TDATA<6><0>
VSS
RSD<6>
RSCLK<6>
RDATA<6><4>
RDATA<6><3>
RDATA<6><2>
RDATA<6><1>
RDATA<6><0>
Fig - 6 Pin Connection Diagram for Management Mode
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AX88850.PDF ] | |
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