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PDF MC14536B Data sheet ( Hoja de datos )
| Número de pieza | MC14536B | |
| Descripción | Programmable Timer | |
| Fabricantes | ON Semiconductor | |
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MC14536B
Programmable Timer
The MC14536B programmable timer is a 24−stage binary ripple
counter with 16 stages selectable by a binary code. Provisions for an
on−chip RC oscillator or an external clock are provided. An on−chip
monostable circuit incorporating a pulse−type output has been
included. By selecting the appropriate counter stage in conjunction
with the appropriate input clock frequency, a variety of timing can be
achieved.
Features
• 24 Flip−Flop Stages − Will Count From 20 to 224
• Last 16 Stages Selectable By Four−Bit Select Code
• 8−Bypass Input Allows Bypassing of First Eight Stages
• Set and Reset Inputs
• Clock Inhibit and Oscillator Inhibit Inputs
• On−Chip RC Oscillator Provisions
• On−Chip Monostable Output Provisions
• Clock Conditioning Circuit Permits Operation with Very Long Rise
and Fall Times
• Test Mode Allows Fast Test Sequence
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load over the Rated Temperature Range
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Rating
Symbol
Value
Unit
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
VDD
Vin,
Vout
Iin, Iout
−0.5 to +18.0
−0.5 to VDD + 0.5
±10
V
V
mA
Power Dissipation per Package (Note 1) PD
500 mW
Ambient Temperature Range
TA
−55 to +125
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Lead Temperature, (8−Second Soldering) TL
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C from 65_C to 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
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1
SOIC−16 WB
DW SUFFIX
CASE 751G
1
SOEIAJ−16
F SUFFIX
CASE 966
1
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
SET
RESET
IN 1
OUT 1
OUT 2
8−BYPASS
CLOCK INH
VSS
1
2
3
4
5
6
7
8
16 VDD
15 MONO−IN
14 OSC INH
13 DECODE
12 D
11 C
10 B
9A
MARKING DIAGRAMS
14536B
AWLYWWG
1
SOIC−16 WB
16
14
536B
ALYWG
G
1
TSSOP−16
MC14536B
ALYWG
1
SOEIAJ−16
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
November, 2014 − Rev. 14
1
Publication Order Number:
MC14536B/D
1 page  
MC14536B
PIN DESCRIPTIONS
INPUTS
SET (Pin 1) −A high on Set asynchronously forces Decode
Out to a high level. This is accomplished by setting an output
conditioning latch to a high level while at the same time
resetting the 24 flip−flop stages. After Set goes low (inactive),
the occurrence of the first negative clock transition on IN1
causes Decode Out to go low. The counter’s flip−flop stages
begin counting on the second negative clock transition of IN1.
When Set is high, the on−chip RC oscillator is disabled. This
allows for very low−power standby operation.
RESET (Pin 2) − A high on Reset asynchronously forces
Decode Out to a low level; all 24 flip−flop stages are also reset
to a low level. Like the Set input, Reset disables the on−chip
RC oscillator for standby operation.
IN1 (Pin 3) −The device’s internal counters advance on the
negative−going edge of this input. IN1 may be used as an
external clock input or used in conjunction with OUT1 and
OUT2 to form an RC oscillator. When an external clock is
used, both OUT1 and OUT2 may be left unconnected or used
to drive 1 LSTTL or several CMOS loads.
8−BYPASS (Pin 6) − A high on this input causes the first 8
flip−flop stages to be bypassed. This device essentially
becomes a 16−stage counter with all 16 stages selectable.
Selection is accomplished by the A, B, C, and D inputs. (See
the truth tables.)
CLOCK INHIBIT (Pin 7) − A high on this input
disconnects the first counter stage from the clocking source.
This holds the present count and inhibits further counting.
However, the clocking source may continue to run.
Therefore, when Clock Inhibit is brought low, no oscillator
startup time is required. When Clock Inhibit is low, the
counter will start counting on the occurrence of the first
negative edge of the clocking source at IN1.
OSC INHIBIT (Pin 14) −A high level on this pin stops the
RC oscillator which allows for very low−power standby
operation. May also be used, in conjunction with an external
clock, with essentially the same results as the Clock Inhibit
input.
MONO−IN (Pin 15) − Used as the timing pin for the
on−chip monostable multivibrator. If the Mono−In input is
connected to VSS, the monostable circuit is disabled, and
Decode Out is directly connected to the selected Q output.
The monostable circuit is enabled if a resistor is connected
between Mono−In and VDD. This resistor and the device’s
internal capacitance will determine the minimum output
pulse widths. With the addition of an external capacitor to
VSS, the pulse width range may be extended. For reliable
operation the resistor value should be limited to the range of
5 kW to 100 kW and the capacitor value should be limited to
a maximum of 1000 pf. (See figures 4, 5, 6, and 11).
A, B, C, D (Pins 9, 10, 11, 12) − These inputs select the
flip−flop stage to be connected to Decode Out. (See the truth
tables.)
OUTPUTS
OUT1, OUT2 (Pin 4, 5) −Outputs used in conjunction with
IN1 to form an RC oscillator. These outputs are buffered and
may be used for 20 frequency division of an external clock.
DECODE OUT (Pin 13) − Output function depends on
configuration. When the monostable circuit is disabled, this
output is a 50% duty cycle square wave during free run.
TEST MODE
The test mode configuration divides the 24 flip−flop
stages into three 8−stage sections to facilitate a fast test
sequence. The test mode is enabled when 8−Bypass, Set and
Reset are at a high level. (See Figure 9.)
TRUTH TABLES
Input
Stage Selected
8−Bypass D C B A for Decode Out
0 0000
9
0 0001
10
0 0010
11
0 0011
12
0 0100
13
0 0101
14
0 0110
15
0 0111
16
0 1000
17
0 1001
18
0 1010
19
0 1011
20
0 1100
21
0 1101
22
0 1110
23
0 1111
24
Input
Stage Selected
8−Bypass D C B A for Decode Out
1 0000
1
1 0001
2
1 0010
3
1 0011
4
1 0100
5
1 0101
6
1 0110
7
1 0111
8
1 1000
9
1 1001
10
1 1010
11
1 1011
12
1 1100
13
1 1101
14
1 1110
15
1 1111
16
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5 Page 
PULSE
GEN.
MC14536B
+V
6 8-BYPASS
9A
10 B
11 C
12 D
2 RESET
14 OSC INH
15 MONO-IN
1 SET
7 CLOCK INH
3 IN1
16
VDD
OUT 1 4
C
OUT 2 5
VSS DECODE OUT 13
8
RS
RTC
RESET
OUT 1
OUT 2
DECODE OUT
fosc
^
1
2.3 Rtc
C
Rs ≥ Rtc
F = Hz
R = Ohms
C = FARADS
POWERUP
tw
NOTE: This circuit is designed to use the on−chip oscillation function. The oscillator frequency is determined by the external R and C
components. When power is first applied to the device, DECODE OUT initializes to a high state. Because this output is tied directly
to the OSC INH input, the oscillator is disabled. This puts the device in a low−current standby condition. The rising edge of the
RESET pulse will cause the output to go low. This in turn causes OSC INH to go low. However, while RESET is high, the oscillator
is still disabled (i.e.: standby condition). After RESET goes low, the output remains low for 2n/2 of the oscillator’s period. After the
part times out, the output again goes high.
Figure 12. Time Interval Configuration Using On−Chip RC Oscillator and
Reset Input to Initiate Time Interval (Divide−by−2 Configured)
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| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet MC14536B.PDF ] | |
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