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PDF CY24130 Data sheet ( Hoja de datos )
| Número de pieza | CY24130 | |
| Descripción | HOTLink SMPTE Receiver Training Clock | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY24130
HOTLink II™ SMPTE Receiver Training Clock
Features
• Integrated phase-locked loop
• Low-jitter, high-accuracy outputs
• 3.3V operation
Benefits
• Internal PLL with up to 400-MHz internal operation
• Meets critical timing requirements in complex system
designs
• Enables application compatibility
Part Number Outputs
CY24130-1
2
CY24130-2
2
Input Frequency
27 MHz (Driven Reference)
27 MHz (Crystal Reference)
Output Frequency Range
1 copy 27-MHz reference clock output
1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)
1 copy 27-MHz reference clock output
1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)
Logic Block Diagram
XIN
XOUT
OSC.
QΦ
VCO
P
PLL
S0
S1
S2
OUTPUT
MULTIPLEXER
AND
DIVIDERS
CLKA
REFCLK
VDDL VDD AVDD AVSS VSS VSSL
Pin Configuration
CY24130-1, -2
16-pin TSSOP
XIN
VDD
AVDD
S0
AVSS
VSSL
N/C
CLKA
1
2
3
4
5
6
7
8
16 XOUT
15 S2
14 REFCLK
13 VSS
12 N/C
11 VDDL
10 S1
9 N/C
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07711 Rev. **
Revised February 04, 2005
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Document History Page
Document Title: CY24130 HOTLink II™ SMPTE Receiver Training Clock
Document Number: 38-07711
REV.
Orig. of
ECN NO. Issue Date Change
Description of Change
**
314514 See ECN
RGL New Data Sheet
CY24130
Document #: 38-07711 Rev. **
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| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet CY24130.PDF ] | |
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