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PDF MC74LVX4245 Data sheet ( Hoja de datos )
| Número de pieza | MC74LVX4245 | |
| Descripción | LOW-VOLTAGE CMOS | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Supply Octal
Translating Transceiver
with 3-State Outputs
The 74LVX4245 is a 24–pin dual–supply, octal translating transceiver
that is designed to interface between a 5V bus and a 3V bus in a mixed
3V/5V supply environment such as laptop computers using a 3.3V CPU
and 5V LCD display. The A port interfaces with the 5V bus; the B port
interfaces with the 3V bus.
The Transmit/Receive (T/R) input determines the direction of data flow.
Transmit (active–High) enables data from the A port to the B port.
Receive (active–Low) enables data from the B port to the A port. The
Output Enable (OE) input, when High, disables both A and B ports by
placing them in 3–State.
• Bi–directional Interface Between 5V and 3V Buses
• Control Inputs Compatible with TTL Level
• 5V Data Flow at A Port and 3V Data Flow at B Port
• Outputs Source/Sink 24mA at 5V Bus and 12mA at 3V Bus
• Guaranteed Simultaneous Switching Noise Level and Dynamic
Threshold Performance
• Available in SOIC and TSSOP Packages
• Functionally Compatible with the 74 Series 245
VCCB VCCB OE B0 B1 B2 B3 B4 B5 B6 B7 GND
24 23 22 21 20 19 18 17 16 15 14 13
MC74LVX4245
LVX
LOW–VOLTAGE CMOS
DW SUFFIX
24–LEAD PLASTIC SOIC PACKAGE
CASE 751E–04
DT SUFFIX
24–LEAD PLASTIC TSSOP PACKAGE
CASE 948H–01
1 2 3 4 5 6 7 8 9 10 11 12
VCCA T/R A0 A1 A2 A3 A4 A5 A6 A7 GND GND
Figure 1. 24–Lead Pinout
(Top View)
PIN NAMES
Pins
Function
OE
T/R
A0–A7
B0–B7
Output Enable Input
Transmit/Receive Input
Side A 3–State Inputs or 3–State
Outputs
Side B 3–State Inputs or 3–State
Outputs
7/97
© Motorola, Inc. 1997
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MC74LVX4245
AC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
TA = –40 to +85°C
CL = 50pF
VCCA = 5V ±0.5V
VCCB = 3.3V ±0.3V
Typ
Min (Note 4.) Max
TA = –40 to +85°C
CL = 50pF
VCCA = 5V ±0.5V
VCCB = 2.7V
Min Max
Unit
tPHL
tPLH
Propagation Delay A to B
1.0 5.1 9.0 1.0 10.0 ns
1.0 5.3 9.0 1.0 10.0
tPHL
tPLH
Propagation Delay B to A
1.0 5.4 9.0 1.0 10.0 ns
1.0 5.5 9.0 1.0 10.0
tPZL
tPZH
Output Enable Time OE to B
1.0 6.5 10.5 1.0 11.5 ns
1.0 6.7 10.5 1.0 11.5
tPZL
tPZH
Output Enable Time OE to A
1.0 5.2 9.5 1.0 10.0 ns
1.0 5.8 9.5 1.0 10.0
tPHZ
tPLZ
Output Disable Time OE to B
1.0 6.0 10.0 1.0 10.0 ns
1.0 3.3 7.0 1.0 7.5
tPHZ
tPLZ
Output Disable Time OE to A
1.0 3.9 7.5 1.0 7.5 ns
1.0 2.9 7.0 1.0 7.5
tOSHL
tOSLH
Output to Output Skew, Data to Output (Note 5.)
1.0 1.5
1.5 ns
4. Typical values at VCCA = 5.0V; VCCB = 3.3V at 25°C.
5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (tOSHL) or LOW–to–HIGH (tOSLH); parameter
guaranteed by design.
Dual Supply Octal Translating Transceiver
The 74LVX4245 is a is a dual–supply device well capable
of bidirectional signal voltage translation. This level shifting
ability provides an excellent interface between low voltage
CPU local bus and a standard 5V I/O bus. The device control
inputs can be controlled by either the low voltage CPU and
core logic or a bus arbitrator with 5V I/O levels.
The LVX4245 is ideal for mixed voltage applications such
as notebook computers using a 3.3V CPU and 5V peripheral
devices.
Applications:
Mixed Mode Dual Supply Interface Solutions
The LVX4245 is designed to solve 3V/5V interfaces when
CMOS devices cannot tolerate I/O levels above their applied
VCC. If an I/O pin of a 3V device is driven by a 5V device, the
P–Channel transistor in the 3V device will conduct — causing
current flow from the I/O bus to the 3V power supply. The
result may be destruction of the 3V device through latchup
effects. A current limiting resistor may be used to prevent
destruction, but it causes speed degradation and needless
power dissipation.
A better solution is provided in the LVX4245. It provides
two different output levels that easily handle the dual voltage
interface. The A port is a dedicated 5V port; the B port is a
dedicated 3V port. Figure 4 on page 6 shows how the
LVX4245 may fit into a mixed 3V/5V system.
Since the LVX4245 is a ‘245 transceiver, the user may
either use it for bidirectional or unidirectional applications.
The center 20 pins are configured to match a ‘245 pinout.
This enables the user to easily replace this level shifter with a
3V ‘245 device without additional layout work or re–
manufacture of the circuit board (when both buses are 3V).
LOW VOLTAGE CPU LOCAL BUS
VCCB
LVX4245
VCCA
VCCB
LVX4245
VCCA
EISA – ISA – MCA
(5V I/O LEVELS)
Figure 3. 3.3V/5V Interface Block Diagram
Powering Up the LVX4245
When powering up the LVX4245, please note that if the
VCCB pin is powered–up well in advance of the VCCA pin,
several milliamps of either ICCA or ICCB current will result. If
the VCCA pin is powered–up in advance of the VCCB pin then
only nanoamps of Icc current will result. In actuality the VCCB
can be powered “slightly” before the VCCA without the current
penalty, but this “setup time” is dependent on the power–up
ramp rate of the VCC pins. With a ramp rate of approximately
50mV/ns (50V/µs) a 25ns setup time was observed (VCCB
LVX Data — Low–Voltage CMOS Logic
BR1492 — Rev 0
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MOTOROLA
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