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PDF MC74LVX374 Data sheet ( Hoja de datos )
| Número de pieza | MC74LVX374 | |
| Descripción | LOW-VOLTAGE CMOS | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal D-Type Flip-Flop
with 3-State Outputs
With 5V-Tolerant Inputs
The MC74LVX374 is an advanced high speed CMOS octal D–type
flip–flop with 3–state outputs. The inputs tolerate voltages up to 7V,
allowing the interface of 5V systems to 3V systems.
This 8–bit D–type flip–flop is controlled by a clock input and an output
enable input. When the output enable input is high, the eight outputs are
in a high impedance state.
• High Speed: fmax = 160MHz (Typ) at VCC = 3.3V
• Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Low Noise: VOLP = 0.8V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
VCC O7 D7 D6 O6 O5 D5 D4 O4 CP
20 19 18 17 16 15 14 13 12 11
MC74LVX374
LVX
LOW–VOLTAGE CMOS
DW SUFFIX
20–LEAD SOIC PACKAGE
CASE 751D–04
DT SUFFIX
20–LEAD TSSOP PACKAGE
CASE 948E–02
1 2 3 4 5 6 7 8 9 10
OE O0 D0 D1 O1 O2 D2 D3 O3 GND
Figure 1. 20–Lead Pinout (Top View)
M SUFFIX
20–LEAD SOIC EIAJ PACKAGE
CASE 967–01
PIN NAMES
Pins
Function
OE
CP
D0–D7
O0–O7
Output Enable Input
Clock Pulse Input
Data Inputs
3–State Outputs
6/97
© Motorola, Inc. 1997
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TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
Symbol
tw
Parameter
Minimum Pulse Width, CP
tsu Minimum Setup Time, D to CP
th Minimum Hold Time, D to CP
MC74LVX374
Test Conditions
VCC = 2.7V
VCC = 3.3 ±0.3V
VCC = 2.7V
VCC = 3.3 ±0.3V
VCC = 2.7V
VCC = 3.3 ±0.3V
TA = 25°C
Typ Limit
7.5
5.0
6.5
4.5
2.0
2.0
TA = – 40
to 85°C
Limit
8.0
5.5
6.5
4.5
2.0
2.0
Unit
ns
ns
ns
CP 50%
tW
1/fmax
tPLH tPHL
O 50% VCC
Figure 3.
D
CP
SWITCHING WAVEFORMS
VCC OE 50%
GND
O
O
VALID
50%
tsu th
50%
Figure 5.
tPZL tPLZ
50% VCC
tPZH tPHZ
50% VCC
Figure 4.
VCC
GND
VCC
GND
VCC
GND
HIGH
IMPEDANCE
VOL +0.3V
VOH –0.3V
HIGH
IMPEDANCE
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
TEST CIRCUITS
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
* Includes all probe and jig capacitance
Figure 6. Propagation Delay Test Circuit
* Includes all probe and jig capacitance
Figure 7. Three–State Test Circuit
LCX DATA
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MOTOROLA
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC74LVX374.PDF ] | |
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