PDF CY7C1387C Data sheet ( Hoja de datos )

Número de pieza	CY7C1387C
Descripción	(CY7C1386C / CY7C1387C) 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com CY7C1386C CY7C1387C 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM Features Functional Description[1] • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200 and 167 MHz • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) • Depth expansion without wait state • 3.3V –5% and +10% core power supply (VDD) • 2.5V / 3.3V I/O operation • Fast clock-to-output times The CY7C1386C/CY7C1387C SRAM integrates 524,288 x 36 and 1048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, a(aEGndndWdarbAe)l.seDAssV-s(p)Cy,ipnEWec2hlriinartoeinnndEgoCnuCaEshb3iilp[ne2p]sE)u,(ntBBsauWbirnlseXct,l(CuaCdonEend1ttr)Bho,WeldienEOpp)utu,httap-senu(xdtApEGDanSnloasCbbioa,lenAl WD(COSrhiEtPipe), and the ZZ pin. — 2.6 ns (for 250-MHz device) — 2.8 ns (for 225-MHz device) — 3.0 ns (for 200-MHz device) — 3.4 ns (for 167-MHz device) Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). • Provide high-performance 3-1-1-1 access rate Address, data inputs, and write controls are registered on-chip • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW • Synchronous self-timed writes • Asynchronous output enable causes all bytes to be written. This device incorporates an www.DataSheaeddt4itiUon.aclopmipelined enable register which delays turning off the output buffers an additional cycle when a deselect is • Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA executed.This feature allows depth expansion without penal- and 165-Ball fBGA packages izing system performance. • IEEE 1149.1 JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode Option The CY7C1386C/CY7C1387C operates from a +3.3V core power supply while all outputs operate with a +3.3V or a +2.5V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide 250 MHz 225 MHz 200 MHz 167 MHz Maximum Access Time 2.6 2.8 3.0 3.4 Maximum Operating Current 350 325 300 275 Maximum CMOS Standby Current 70 70 70 70 Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Notes: 1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. CE3 and CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in Single Chip Enable. Unit ns mA mA Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-05239 Rev. B Revised February 26, 2004 www.DataSheet4U.com 1 page www.DataSheet4U.com Pin Configurations (continued) 123 A NC / 288M A B NC A C DQPC NC D DQC DQC CE1 CE2 VDDQ VDDQ E DQC DQC VDDQ F DQC DQC VDDQ G DQC DQC VDDQ H NC VSS NC J DQD DQD VDDQ K DQD DQD VDDQ L DQD DQD VDDQ M DQD DQD VDDQ N DQPD NC VDDQ P NC NC / 72M A R MODE NC / 36M A 123 A NC / 288M A B NC A C NC NC D NC DQB CE1 CE2 VDDQ VDDQ E NC DQB VDDQ F NC DQB VDDQ G NC DQB VDDQ H NC VSS NC J DQB NC VDDQ K DQB NC VDDQ L DQB NC VDDQ M DQB NC VDDQ N DQPB NC VDDQ P NC NC / 72M A R MODE NC / 36M A CY7C1386C CY7C1387C 165-ball fBGA (3 Chip Enable) CY7C1386C (512K x 36) 4 567 BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO A TMS A0 TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A CY7C1387C (1M x 18) 4www.Da5taShee6t4U.com7 BWB NC CE3 BWE NC BWA CLK GW VSS VSS VSS VSS VDD VSS VSS VSS VDD VSS VSS VSS VDD VSS VSS VSS VDD VSS VSS VSS VDD VSS VSS VSS VDD ‘VSS VSS VSS VDD VSS VSS VSS VDD VSS VSS VSS VDD VSS VSS VSS VSS NC A NC A TDI A1 TDO A TMS A0 TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 11 A NC A NC / 144M NC DQB DQB DQB DQB NC DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA NC A DQA DQA DQA DQA DQPA A AA 10 11 AA A NC / 144M NC DQPA NC DQA NC DQA NC DQA NC DQA NC ZZ DQA NC DQA NC DQA NC DQA NC NC NC AA AA Document #: 38-05239 Rev. B www.DataSheet4U.com Page 5 of 34 5 Page www.DataSheet4U.com CY7C1386C CY7C1387C Functional Overview The write signals (GW, ignored during this first BWE, cycle. and BWX) and ADV inputs are All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1386C/CY7C1387C supports secondary cache in ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corre- sponding address location in the memory core. If GW is HIGH, systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 then the write operation is controlled signals. The CY7C1386C/CY7C1387C by BWE provides and byte BwWriteX processors. The linear burst sequence is suited for processors capability that is described in the Write Cycle Description table. that utilize a linear burst sequence. The burst order is user Asserting the Byte Write Enable input (BWE) with the selected selectable, and is determined by sampling the MODE input. Byte Write input will selectively write to only the desired bytes. Accesses can be initiated with either the Processor Address Bytes not selected during a byte write operation will remain Strobe (ADSP) or the Controller Address Strobe (ADSC). unaltered. A synchronous self-timed write mechanism has Address advancement through the burst sequence is been provided to simplify the write operations. controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Because the CY7C1386C/CY7C1387C is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will tri-state the output drivers. As a safety precaution, DQ are automati- Byte write operations are qualified with the Byte Write Enable cally tri-stated whenever a write cycle is detected, regardless (BWE) and Byte Write Select (BWX) inputs. A Global Write of the state of OE. Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip Single Write Accesses Initiated by ADSC synchronous self-timed write circuitry. ADSC write accesses are initiated when the following condi- Synchronous Chip Selects CE1, CE2, CE3[2] and an asynchronous Output Enable (OE) provide for easy bank selection is HIGH. and output tri-state control. ADSP is ignored if CE1 tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, abyntdeB(sW). XA)DaSreCatsrisgegretereddawctrivitee to conduct a write accesses require to the desired a single clock Single Read Accesses cycle to complete. The address presented is loaded into the TsisRsOc(sGpthaheouoitWiHpgrtisspneiI,sfudsdGiateBetiencHdiWlRnrecg.awteecEottsTgdhs)csiathishlalaetoetaeriercseberkaaesiasidadr.innlidlldsAilagtrderitaleaelpe:otsstsh(raewss1esesde)sesaprreAdetiwdrsenDrevihdtttnseeoaSegeddanPnnpccetHtootredetioIvhrmgtGdpheeAeeaHe,Dtngoofa.moStafnAltteCltldeohohDmgewei(Ssti3oiocnPnar)aeygasdttixhshcsndtceoeedwricgoerrlwetnntsoiwenh.sodrcdpeTiwkrittueeLhiinAottd.OehspDndeociWiusdgffoatdrnCs,reatatar(hEsare2tlieeasss1-)Sheabltwswdpeoheuderrrceteliirid4afttnisee-snrttgeUeeiigomonsldenp.osteeteccehpidldtnoririeevesawtremdtgotahirrcoibteeitsiythnyoetdcmeestneltmr.eDeos.ameQtawnhcIorfXihdeelrlaiyasmwtnhcwrreigeesoitmrlmtmroieteaotbnae.dhra.inIydnaflBrsicaneywobtstubroreseienytstee.athaennTletdoiehwspvctrerraoesoictnerAdevorcl.eDiendeisscdVempAtucdeoiecondntntnpoesddtdudyiusnutln,origicmicsgntthhaeipgicgreddloiandf,wnyodrbooehrtaynehusittlledeaeyss is allowed to propagate through the output register and onto Because the CY7C1386C/CY7C1387C is a common I/O the data bus within tco if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQX inputs. Doing so will tri-state the output drivers. As a safety precaution, DQX are automati- cally tri-stated whenever a write cycle is detected, regardless outputs are controlled by the OE signal. Consecutive single of the state of OE. read cycles are supported. The CY7C1386C/CY7C1387C is a double-cycle deselect part. Burst Sequences Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately after the next clock rise. The CY7C1386C/CY7C1387CCY7C1387C provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address sequence is designed specifically to support Intel® Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Both read and write burst operations are supported. advancement logic while being delivered to the memory core. Document #: 38-05239 Rev. *B www.DataSheet4U.com Page 11 of 34 11 Page

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