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PDF LTC2249 Data sheet ( Hoja de datos )
| Número de pieza | LTC2249 | |
| Descripción | 80Msps Low Power 3V ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC2249
14-Bit, 80Msps
Low Power 3V ADC
FEATURES
DESCRIPTIO
■ Sample Rate: 80Msps
The LTC®2249 is a 14-bit 80Msps, low power 3V A/D
■ Single 3V Supply (2.7V to 3.4V)
converter designed for digitizing high frequency, wide
■ Low Power: 222mW
dynamic range signals. The LTC2249 is perfect for de-
■ 73dB SNR at 70MHz Input
manding imaging and communications applications with
■ 90dB SFDR at 70MHz Input
AC performance that includes 73dB SNR and 90dB SFDR
■ No Missing Codes
for signals well beyond the Nyquist frequency.
■ Flexible Input: 1VP-P to 2VP-P Range
■ 575MHz Full Power Bandwidth S/H
■ Clock Duty Cycle Stabilizer
■ Shutdown and Nap Modes
DC specs include ±1LSB INL (typ), ±0.5LSB DNL (typ) and
no missing codes over temperature. The transition noise
is a low 1.2LSBRMS.
■ Pin Compatible Family
A single 3V supply allows low power operation. A separate
80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit)
output supply allows the outputs to drive 0.5V to 3.3V
65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit)
logic.
40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit)
A single-ended CLK input controls converter operation. An
25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit)
optional clock duty cycle stabilizer allows high perfor-
10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit)
mance at full speed for a wide range of clock duty cycles. DataShee
■ 32-Pin (5mm × 5mm) QFN Package
U DataSheet4U,.cLToCmand LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
■ Wireless and Wired Broadband Communication
■ Imaging Systems
■ Ultrasound
■ Spectral Analysis
■ Portable Instrumentation
TYPICAL APPLICATIO
REFH
REFL
FLEXIBLE
REFERENCE
ANALOG
INPUT
+
INPUT
S/H
–
14-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
DataSheet4U.com
CLK
CORRECTION
LOGIC
OUTPUT
DRIVERS
OVDD
D13
•
•
•
D0
OGND
2229 TA01
SNR vs Input Frequency,
–1dB, 2V Range
75
74
73
72
71
70
69
68
67
66
65
0 50 100 150 200
INPUT FREQUENCY (MHz)
2249 G09
2249f
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LTC2249
WU
TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
fs
tL
PARAMETER
Sampling Frequency
CLK Low Time
tH CLK High Time
tAP
tD
Pipeline
Latency
Sample-and-Hold Aperture Delay
CLK to DATA Delay
Data Access Time After OE↓
BUS Relinquish Time
CONDITIONS
(Note 9)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On (Note 7)
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On (Note 7)
CL = 5pF (Note 7)
CL = 5pF (Note 7)
(Note 7)
MIN TYP MAX
●1
80
● 5.9 6.25 500
● 5 6.25 500
● 5.9 6.25 500
● 5 6.25 500
0
● 1.4 2.7 5.4
● 4.3 10
● 3.3 8.5
6
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
Note 1: Absolute Maximum Ratings are those values beyond which the life Note 5: Integral nonlinearity is defined as the deviation of a code from a
of a device may be impaired.
straight line passing through the actual endpoints of the transfer curve.
Note 2: All voltage values are with respect to ground with GND and OGND The deviation is measured from the center of the quantization band.
wired together (unless otherwise noted).
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
the output code flickers between 00 0000 0000 0000 and
11 1111 1111 1111.
et4U.com
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 80MHz, input range = 2VP-P with differential
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 80MHz, input range = 1VP-P with
drive, unless otherwise noted.
differential drive.
DataSheet4NUot.ec9o:mRecommended operating conditions.
DataShee
TYPICAL PERFOR A CE CHARACTERISTICS
Typical INL, 2V Range
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
4096
8192
CODE
12288 16384
2249 G01
Typical DNL, 2V Range
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
4096
8192
CODE
12288
16384
2249 G02
8192 Point FFT, fIN = 5MHz,
–1dB, 2V Range
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5 10 15 20 25 30 35 40
FREQUENCY (MHz)
2249 G03
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2249f
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LTC2249
APPLICATIO S I FOR ATIO
high to low, the inputs are reconnected to the sampling For the best performance, it is recommended to have a
capacitors to acquire a new sample. Since the sampling source impedance of 100Ω or less for each input. The
capacitors still hold the previous sample, a charging glitch source impedance should be matched for the differential
proportional to the change in voltage between samples will inputs. Poor matching will result in higher even order
be seen at this time. If the change between the last sample harmonics, especially the second.
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as Input Drive Circuits
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Figure 3 shows the LTC2249 being driven by an RF
transformer with a center tapped secondary. The second-
Single-Ended Input
ary center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Terminating on the trans-
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, AIN+
should be driven with the input signal and AIN– should be
connected to 1.5V or VCM.
former secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen by
the ADC does not exceed 100Ω for each ADC input. A
disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
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Common Mode Bias
poor performance at frequencies below 1MHz.
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differential driver circuit. The VCM pin must be bypassed to
ground close to the ADC with a 2.2µF or greater capacitor.
Input Drive Impedance
0.1µF T1
ANALOG
1:1
INPUT
25Ω
25Ω 0.1µF
VCM
2.2µF
AIN+
LTC2249
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2249 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and reactance can
25Ω
T1 = MA/COM ETC1-1T 25Ω
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
12pF
AIN–
2249 F03
influence SFDR. At the falling edge of CLK, the sample-
and-hold circuit will connect the 4pF sampling capacitor to
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
the input pin and start the sampling period. The sampling
period ends when CLK rises, holding the sampled input on
VCM
the sampling capacitor. Ideally the input circuitry should
be fast enough to fully charge the sampling capacitor
during the sampling period 1/(2FENCODE); however, this is
not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER 25Ω
++
CM
––
25Ω
2.2µF
AIN+
LTC2249
12pF
AIN–
to be as linear as possible to minimize the effects of
DataSheetin4cUo.cmopmlete settling.
2249 F04
Figure 4. Differential Drive with an Amplifier
2249f
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| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC2249.PDF ] | |
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