PDF CYS25G0101DX Data sheet ( Hoja de datos )

Número de pieza	CYS25G0101DX
Descripción	SONET OC-48 Transceiver
Fabricantes	Cypress Semiconductor
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No Preview Available ! www.DataSheet4U.com CYS25G0101DX SONET OC-48 Transceiver Features • SONET OC-48 operation • Bellcore and ITU jitter compliance • 2.488-GBaud serial signaling rate • Multiple selectable loopback/loop-through modes • Single 155.52-MHz reference clock • Transmit FIFO for flexible data interface clocking • 16-bit parallel-to-serial conversion in transmit path • Serial-to-16-bit parallel conversion in receive path data recovery operations in a single chip, optimized for full SONET compliance. Transmit Path New data is accepted at the 16-bit parallel transmit interface at a rate of 155.52 MHz. This data is passed to a small integrated FIFO to allow flexible transfer of data between the SONET processor and the transmit serializer. As each 16-bit word is read from the transmit FIFO, it is serialized and sent out the high-speed differential line driver at a rate of 2.488 Gbits/second. • Synchronous parallel interface Receive Path — LVPECL-compliant As serial data is received at the differential line receiver, it is — HSTL-compliant passed to a clock and data recovery (CDR) PLL, which • Internal transmit and receive phase-locked loops (PLLs) extracts a precision low-jitter clock from the transitions in the data stream. This bit-rate clock is then used to sample the data • Differential CML serial input stream and receive the data. Every 16-bit-times, a new word is presented at the receive parallel interface along with a clock. — 50-mV input sensitivity — 100Ω Internal termination and DC-restoration Parallel Interface • Differential CML serial output The parallel I/O interface supports high-speed bus communi- cations using HSTL signaling levels to minimize both power — Source matched for 50Ω transmission lines (100Ω consumption and board landscape. The HSTL outputs are • differential transmission Direct interface to standard lines) fiber-optic modulesDataSheet4c7Ua0p.macbomlme, oafnddritveirnmgiunnatteerdm5in0aΩtetdratnrasnmsimssisiosniolninleinseosfomf loerses than than • Less than 1.0W typical power twice that length. • 120-pin 14 mm × 14 mm TQFP The CYS25G0101DX Transceiver’s parallel HSTL I/O can • Standby power-saving mode for inactive loops • 0.25µ BiCMOS technology also be configured to operate at LVPECL signaling levels. This can all be done externally by changing VDDQ, VREF, and creating a simple circuit at the termination of the transceiver’s Functional Description parallel output interface. The CYS25G0101DX SONET OC-48 Transceiver is a communications building block for high-speed SONET data communications. It provides complete parallel-to-serial and serial-to-parallel conversion, clock generation, and clock and Clocking The source clock for the transmit data path is selectable from either the recovered clock or an external BITS (Building Integrated Timing Source) reference clock. The low jitter of the DataShee SONET Data CYS25G0101DX 16 Processor TXD[15:0] TXCLKI Transmit Data Interface FIFO_RST FIFO_ERR TXCLKO REFCLK± 2 155.52 MHz BITS Time Host Bus Receive Data 16 RXD[15:0] Reference Interface Interface RXCLK Data & Clock Direction Control LOOPTIME DIAGLOOP LOOPA LINELOOP IN+ IN– SD OUT– OUT+ Serial Data Serial Data RD+ RD– SD TD– Optical XCVR TD+ Status and System Control RESET PWRDN LOCKREF LFI Figure 1. CYS25G0101DX System Connections Optical Fiber Links DataSheet4U.com Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-02009 Rev. J Revised December 30, 2002 DataSheet4 U .com 1 page www.DataSheet4U.com CYS25G0101DX et4U.com CYS25G0101DX OC-48 SONET Transceiver (continued) Pin Name I/O Characteristics Signal Description LINELOOP LVTTL input Line Loopback Control. When HIGH, received serial data is looped back from receive to transmit after being reclocked by a recovered clock. When LINELOOP is LOW, the data passed to the OUT± line driver is controlled by LOOPA. When both LINELOOP and LOOPA are LOW, the data passed to the OUT± line driver is generated in the transmit shifter. LOOPA LVTTL input Analog Line Loopback. When LINELOOP is LOW and LOOPA is HIGH, received serial data is looped back from receive input buffer to transmit output buffer, but is not routed through the clock and data recovery PLL. When LOOPA is LOW, the data passed to the OUT± line driver is controlled by LINELOOP. LOOPTIME LVTTL input Loop Time Mode. When HIGH, the extracted receive bit-clock replaces transmit bit-clock. When LOW, the REFCLK input is multiplied by 16 to generate the transmit bit clock. Serial I/O OUT± Differential CML output Differential Serial Data Output. This differential CML output (+3.3V referenced) is capable of driving terminated 50Ω transmission lines or commercial fiber-optic transmitter modules. IN± Differential CML Differential Serial Data Input. This differential input accept the serial data stream for input deserialization and clock extraction. Power VCCN VSSN VCCQ VSSQ VDDQ Power Ground Power Ground Power +3.3V supply (for digital and low-speed I/O functions) Signal and power ground (for digital and low-speed I/O functions) +3.3V quiet power (for analog functions) Quiet ground (for analog functions) +1.5V supply for HSTL outputs[4] CYS25G0101DX Operation the transmit FIFO has either under or overflowed. The FIFO can be externally reset to clear the error indication or if no The CYS25G0101DX is a highly configurable device dDeasitganSehdeet4aUc.tcioonmis taken, the internal clearing mechanism will clear the to support reliable transfer of large quantities of data using FIFO in nine clock cycles. When the FIFO is being reset, the high-speed serial links. It performs necessary clock and data output data is 1010. recovery, clock generation, serial-to-parallel conversion, and parallel-to-serial conversion. CYS25G0101DX also provides Transmit PLL Clock Multiplier various loopback functions. The Transmit PLL Clock Multiplier accepts a 155.52-MHz CYS25G0101DX Transmit Data Path external clock at the REFCLK input, and multiplies that clock by 16 to generate a bit-rate clock for use by the transmit shifter. Operating Modes The operating serial signaling rate and allowable range of REFCLK frequencies is listed in Table 7. The REFCLK phase The transmit path of the CYS25G0101DX supports 16-bit noise limits to meet SONET compliancy are illustrated in -wide data paths. Figure 5. The REFCLK± input is a standard LVPECL input. DataShee Phase-Align Buffer Data from the input register is passed to a phase-align buffer (FIFO). This buffer is used to absorb clock phase differences between the transmit input clock and the internal character clock. Initialization of the phase-align buffer takes place when the FIFO_RST input is asserted LOW. When FIFO_RST is returned HIGH, the present input clock phase relative to TXCLKO is set. Once set, the input clock is allowed to skew in time up to half a character period in either direction relative to REFCLK (i.e., ±180°). This time shift allows the delay path of the character clock (relative to REFLCK) to change due to operating voltage and temperature while not effecting the desired operation. FIFO_RST is an asynchronous input. FIFO_ERR is the transmit FIFO Error indicator. When HIGH, Note: 4. VDDQ equals VCC if interfacing to a parallel LVPECL interface. Serializer The parallel data from the phase-align buffer is passed to the Serializer which converts the parallel data to serial data using the bit-rate clock generated by the Transmit PLL clock multi- plier. TXD[15] is the most significant bit of the output word, and is transmitted first on the serial interface. Serial Output Driver The serial interface Output Driver makes use of high-perfor- mance differential Current Mode Logic (CML) to provide a source-matched driver for the transmission lines. This driver receives its data from the Transmit Shifters or the receive loopback data. The outputs have signal swings equivalent to that of standard LVPECL drivers, and are capable of driving AC-coupled optical modules or transmission lines. DataSheet4U.com Document #: 38-02009 Rev. J DataSheet4 U .com Page 5 of 15 5 Page www.DataSheet4U.com Jitter Waveforms CYS25G0101DX et4U.com Figure 3. Jitter Transfer Waveform of CYS25G0101DX[12] DataSheet4U.com Figure 4. Jitter Tolerance Waveform of CYS25G0101DX[12] Note: 12. The bench jitter measurements were performed using an Agilent Omni-bert SONET jitter tester. DataShee DataSheet4U.com Document #: 38-02009 Rev. *J DataSheet4 U .com Page 11 of 15 11 Page

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