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PDF AM49DL640BG Data sheet ( Hoja de datos )
| Número de pieza | AM49DL640BG | |
| Descripción | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM | |
| Fabricantes | SPANSION | |
| Logotipo |  |
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Am49DL640BG
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
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Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
DataShee
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Publication Number 26090 Revision A Amendment 0 Issue Date March 8, 2002
1 page  
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PRELIMINARY
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 57
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 57
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 57
pSRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 58
pSRAM Power on and Deep Power Down . . . . . 58
Figure 33. Deep Power-down Timing.............................................. 58
Figure 34. Power-on Timing............................................................ 58
pSRAM Address Skew . . . . . . . . . . . . . . . . . . . . . 59
Figure 35. Read Address Skew ..................................................... 59
Figure 36. Write Address Skew...................................................... 59
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 60
FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 60
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 61
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Am49DL640BG
March 8, 2002
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PRELIMINARY
MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Tables 1-2 lists the device bus operations, the
inputs and control levels they require, and the result-
ing output. The following subsections describe each of
these operations in further detail.
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Operation
(Notes 1, 2)
Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH
CE#f CE1#s CE2s OE# WE#
Address
LB#s
UB#s RESET#
WP#/ACC
(Note 4)
Read from
Flash
(Note 7)
(Note 8)
L
H
H
H
LH
L
AIN
XX
H
L/H
(Note 7)
HH
Write to Flash
L
HL
(Note 8)
HL
AIN
XX
H (Note 4)
Standby
VCC ±
0.3 V
H
H XX
X
X X VCC ±
0.3 V
H
Deep Power-down
Standby
VCC ±
0.3 V
H
L XX
X
X X VCC ±
0.3 V
H
Output Disable
HH
L LH
HH
X
X
XX
XX
H
L/H
Flash Hardware (Note 7)
Reset
(Note 8)
X
H
H
H
XX
L
X
XX
L
L/H
Sector Protect (Note 7)
(Note 5)
(Note 8)
L
H
H
H
L
H
L
SADD, A6 = L,
A1 = H, A0 = L
X
X
VID
L/H
Sector
Unprotect
(Note 5)
(Note 7)
(Note 8)
L
H
H
H
L
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H
L
SADD, A6 = H,
A1 = H, A0 = L
X
X
VID (Note 6)
Temporary
(Note 7)
HH
Sector
X
XX
Unprotect
(Note 8)
HL
X
X X VID (Note 6)
LL
Read from pSRAM
H L H LH
AIN
HL
LH
H
X
LL
Write to pSRAM
H L H XL
AIN
HL
H
X
LH
DQ7–
DQ0
DOUT
DIN
High-Z
High-Z
High-Z
High-Z
DIN
DIN
DIN
DOUT
High-Z
DOUT
DIN
High-Z
DIN
DQ15–
DQ8
DOUT
DIN
High-Z
High-Z
High-Z
High-Z
X
X
High-Z
DOUT
DOUT
High-Z
DIN
DIN
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = pSRAM Address Input, Byte Mode,
SADD = Flash Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Other operations except for those indicated in this column are
inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same
time.
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC
= VIH the boot sectors protection will be removed.
If WP#/ACC = VACC (9V), the program time will be reduced by
40%.
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5. The sector protect and sector unprotect functions may also be
implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
6. If WP#/ACC = VIL, the two outermost boot sectors remain
protected. If WP#/ACC = VIH, the two outermost boot sector
protection depends on whether they were last protected or
unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If WP#/ACC = VHH, all sectors will
be unprotected.
7. Data will be retained in pSRAM.
8. Data will be lost in pSRAM.
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Am49DL640BG
March 8, 2002
11 Page | ||
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